ADSD Fall 2011

Lecture # 08

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011

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http://lms.nust.edu.pk/
Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti 2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan 3. [STV] Advanced FPGA Design, Steve Kilts 4. Ercegovacs Book: Digital Arithmetic 2004 5. Dr. Shoab A Khans CASE Lectures on Advanced Digital System Design
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

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Introduction Verilog+ Combinational Logic Verilog + Sequential Logic Synthesis in Verilog Micro-Architecture <Micro-Coded-Machines> Optimizing Speed Optimizing Area FIR Implementation CDC Issues Fixed-Point Arithmetic Adders Multipliers CORDIC Algorithmic Transformations for System Design Algorithmic Transformations Project Project

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Outline & Introduction, Initial Assessment of students, Digital design methodology & design flow Combinational Logic Review + Verilog Introduction, Combinational Building Blocks in Verilog Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS), Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements Design Partitioning + RISC Microprocessor + Micro architecture Document Architecting Speed in Digital System Design: [Throughput, Latency, Timing] Architecting Area in Digital System Design: [Area Optimization] FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs Cross-Clock Domain Issues & RESET circuits Arithmetic Operations: Review Fixed Point Representation Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW DFG representation of DSP Algorithms, Iteration Bound & Retiming

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Unfolding Look ahead transformations Course Review & Project Presentations

Project Presentations

Lecture Overview
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Algorithms,

Arithmetic & Numbers 2s Complement Representation Generating Overflow Flag Fixed point / Floating point Qn.m format Truncating/ Rounding

Algorithms in Hardware
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Primitives
Addition/subtraction
Multi

operand addition Logical and arithmetic shift Multiplication by constant Multiplication Division

Algorithms
Sequenced Composition

of Primitives

Numbers in hardware
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Number Signed Number Positive Number Unsigned Numbers

Negative Number

Representing Numbers
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n-bit unsigned Binary Numbers

B

= bn-1, bn-2,.., b1, b0 with bi from {0,1}

Negative Number Representation

Signed

Magnitude Ones Complement Twos Complement

Signed Magnitude
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Designate left-most bit as a sign bit with no arithmetic weight 1-> negative, 0-> positive. Positive and negative zero (0000 vs. 1000) Difficult to add numbers of different sign or subtract numbers of same sign (comparison)

Same sign bits Add and use same sign Different signs Logic to decide add or sub & final sign

N-1 bits are available to represent magnitude Range of N-bit signed-magnitude number is: -(2N-1 1) to (2N-1 1)

[CIL]

Ones Complement
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Flipped bits as negative number Positive and negative zero (0000 vs. 1000) Subtraction is more complicated than in 2scomp Range of N-bit signedmagnitude number is:

-(2N-1 1) to (2N-1 1)

Twos Complement
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Unified Representation for both positive & negative numbers in 2s Complement

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Equivalent unsigned representation

Example
For N=8, -10 b11110110 For N=5, -10 b10110

Paper & Pencil conversion by scanning from right to left, leaving the first one and flipping all the remaining bits

Twos Complement
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Arithmetic
+,

-, *, / performed in hardware with a unit that can carry out binary operations of addition and bitwise complement.
Addition: Same hardware as

reduced dynamic range Subtraction: Bitwise complements and addition of one and a number ! Multiplication: Repeated additions Division involves repeated subtraction Negative of a number : Complement & add 1

binary numbers but

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Addition in 2s Complement

Addition/Subtraction in 2s Complement
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Addition in 2s Complement (a+b)

Normal

Binary Addition (a+b)

Subtraction in 2s Complement (a-b)

Equivalent

to Normal Binary Addition with (a+(-b)) Rather than subtracting add the negative of the number Example: (-10)-(10)

Drop the Carry outs

Negating a number in HW
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Addition of number similar to unsigned binary addition Flip all the bits & Add ONE

Problem Need a Carry Propagate Adder

Solution: Full Adders

Overflow issue due to asymmetric range

Example: Negative of 1000

Adder/Subtractor for 2s Complement

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Knowing Overflow

Signed and Unsigned Integers A Hardware Viewpoint

Hardware cannot distinguish between signed and unsigned integers YOU are solely responsible for using the correct data type with each instruction Verilog does not provide synthesizable signed representation
Consider

an adder adding two 2s complement

numbers

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Overflow Examples
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overflow occurs when: POS+POS=NEG or NEG+NEG=POS

+3 0011 +4 0100 -------+7 0111 -5 1011 +6 0110 -------+1 0001

+5 0101 +6 0110 -------+11 1011

(signed overflow but not an unsigned overflow)

+5 0101 -6 1010 --------1 1111 -5 1011 -6 1010 --------11 0101

(unsigned & signed overflow)

-3 1101 -4 1100 --------7 1001

Overflow and Carry Flags A Hardware Viewpoint

Overflow Unsigned
Carry

Out of MSB

2s Complement
Carryout
OF

does not indicate overflow ADDITION

= (carry out of the MSB) XOR (carry into the MSB)
SUBTRACTON
NEG the source and ADD

it to the destination OF = (carry out of the MSB) XOR (carry into the MSB)
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Knowing your 2s Complement Number for Corner Cases (Because of the slightly asymmetric range, negation may lead to overflow! )
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Corner Cases
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There is no equal opposite of -2N-1 in N bits 2s complement representation For example, while multiplying two ve numbers like -4 x -4 , we can get 16 and we cant represent this as a 5-bit 2s complement No.

Knowing if a number is Negative

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S(N-1) is the MSB of the Sum

Generating the Flags

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Needs Correction
<Unsigned overflow>

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Fixed Point Representation

Most computational algorithms require fractional numbers

Floating Point Numbers

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Representing Fixed Point Numbers

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Insert implicit binary point between two bits

bits to left of point have value 1 bits to right of point have value < 1
binary point

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(512) (256) (128) (64) (32) (16) (8) (4) (2) (1) (0.5) (0.25) (0.0625) (0.015625) (0.125) (0.03125)

0 1 0 0 0 0 1 1 0 1.0 1 1 1 1 0 269.46875

Qn.m Format
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Qn.m format is a fixed positional number system for representing floating-point numbers Qn.m simply means that N-bit binary number has n bits to the left and m bits to the right of the binary point
In

case of signed-numbers the MSB is used for sign

There is NO Decimal in HW
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1.

Define the total No. of bits to represent a No. (Lets say 10 bits)

2.

Fix a Decimal some where in the No. -21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 (Lets say after 2 locations) Note that there is no decimal in H/W.

Sign Bit Zeroth Bit

Fractional Bits

Floating Point to Fixed Point Conversion

In Qn.m format,
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n depends upon the range of our required integer m depends upon how much precision we want in the fractional part of our computation.

Q3.13
Example 1 bit for the sign and 2 bits are reserved for the integer part 13 bits are reserved for the fractional part

Floating Point to Fixed Point Conversion

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The algorithm is analyzed for all set of inputs Range of each variable is observed Depending upon the precision required, n and m are specified. For implementation on programmable processors, N=16, or 32 For Application Specific Hardware, an optimal value of N is specified.

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Example Optimization: Different blocks can have different range/precision requirement

Speech Samples

AGC

Filter

Q1.17 Format

Q9.12 Format
At every point, we check the ranges Compress

Q3.18 Format

O/p

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Arithmetic in Q Format

Addition in Q Format
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Adding 2 different Qn.m Format numbers we get

Q=QMax(n1,n2) +

Max(m1.m2)

Addition in Q Format
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If two numbers a and b of Qn1.m1 and Qn2.m2 formats respectively are added, the result is in Qn.m format, where n is larger of n1 and n2 and m is larger of m1 and m2.
Example Implied Decimal

Qn1.m1 = Qn2.m2 = 0

0 0 1 0 1 1 1 0 1 1 0

Q2.2 Q4.4

Qn.m =

0 1 1 1 1 1 1 0

Q4.4

Sign Extension
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We need to extend the sign bit to its left. Copying the sign bit to its left doesnt change the original value of the number

Addition in Q Format
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If two numbers a and b of Qn1.m1 and Qn2.m2 formats respectively are added, the result is in Qn.m format, where n is larger of n1 and n2 and m is larger of m1 and m2.
Example Implied Decimal Q2.2 = - 2 + 1 + 0.5 = -0.5 Q4.4 = 1 + 2+ 4 + 0.25 + 0.125 = 7.375

Qn1.m1 = 1 Qn2.m2 = 0

1 1 1 1 0 1 1 1 0 1 1 0

Qn.m =

0 1 1 0 1 1 1 0

Q4.4 = 2 + 4+ 0.5 + 0.25 + 0.125 = 6.875

May Require Extension of Fixed Point Numbers

Bit Growth
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Due the demand for increased number of bits effective Width of the words will increase

Multiplication in Q-Format
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c=axb
Q n1.m1 Q n2.m2
(a) (b)

Q (n1+n2) . (m1+m2) ( c )

Rounding & Truncating

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Truncation
Simple Truncate An operation similar to floor

Rounding

Or ADD a copy of bit after the truncation point to itself

Rounding Vs. Truncation

Rounding basically weighted truncation. Algorithmically it is better to round and then truncate in H/W. Resource-wise Rounding adds overhead

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Thanks