AF4004

AF4004
OC-12/STM-4 EoE1oSDH Framer-Mapper
Rev. 1.0 Sep 2010 Preliminary Short Data Sheet

GENERAL DESCRIPTION
The AF4004 provides a Ethernet over E1 over SONET/SDH mapping. The 252 E1s frame can be mapped to VT2/TU12 to SONET/SDH transport. The chip supports a Dual OC-12/STM-4 SONET/SDH interface with 1+1/1:1 Linear APS protection or UPSR/SNCP protection. On the Ethernet side, the chip provides 2 (1+1 protection) Ethernet/Fast Ethernets via SMII/SS-SMII interface and/or 2 (1+1 protection) Ethernet/Fast/Gigabit Ethernet ports via SGMII interface with on-chip CDRs. The AF4004 supports PPP/HDLC/LAPS and GFP encapsulation with up to 252 channels. A MAC-Learning/Aging Engine using Hash Table to do forwarding function for packets received from Ethernet lines.

KEY FEATURES

Two 10/100Mpbs Ethernet ports via SMII/SS-SMII Two 10/100/1000Mbps Ethernet ports via SGMII with on-chip CDR Dual OC-12/STM-4 ports with on-chip CDR Ethernet MAC controller with flow control as 802.3x OAM and statistical counters: Byte counters and Frame counters Per Port and Queue PPP/HDLC/ LAPS and GFP encapsulation 252 E1 unframe, basic frame or CRC-4 multi-frame framers Mapping of 252 E1 to SONET/SDH 2x16Mx16 DDR2 SDRAM for packet buffer FPGA package size 23x23mm 484-Pin FBGA Power consumption less than 3.5W

APPLICATIONS

Ethernet over E1 over SONET/SDH Pizza Box with E/FE/GE Interface Ethernet over E1 over SONET/SDH Line Card with E/FE/GE Interface

SMII/ SS-SMII Dual OC-12/ STM-4 UPSR, 1+1

Ethernet PHY

2x10/100 Ethernet

SFP Optical Module

SONET/SDH CDR Interface

AF4004

GbE CDR Interface

GbE SFP

2Gb Ethernet

Packet DDR2 SDRAM

AF4004 BLOCK DIAGRAM

BITS Timing 1-Wire Host CPU Bus JTAG

Clock Synthesizer

Key Management

uP interface

JTAG Interface

2 x Serial 622.08Mbps

2 x Rx OC-12/STM-4 SerDes

Two SONET/SDH Framer Transport Overhead Processor

2xSTS-12 HO/LO Pointer Processor Alarm Monitor 2xSTS-12 HO/LO Pointer Generator STS/AU VT/TU Multi-Level Cross-Connect PDH Sub-system 2xE/FE 10/100Mbps 1+1 2xE/FE/GE 10/100/1000Mbps 1+1 252 TU12/VC12 Map/DeMap 252 E1 Tx/Rx Framer E1 Alarm

2 x Serial 622.08Mbps

2 x Tx OC-12/STM-4 SerDes

1+1/1:1 HW-APS

UPSR HW-APS

BER Monitor

Path Overhead Termination

APS Processor

POH Processor

252 PPP/HDLC LAPS/GFP Encapsulation

MAC Learning/ Aging Processor

MAC Controller

SMII/ SS-SMII SGMII SerDes

SONET/SDH Sub-system OH Drop/Insert Bus CMF/OAM Buffer Packet DDR2 SDRAM Controller RMON Statistic Counters MDIO Interface Packet Sub-system OH Access Data Link Access 2x16-Bit@DDR2 SDRAM

Data Link Controller

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AF4004
AF4004
OC-12/STM-4 EoE1oSDH Framer-Mapper
Rev. 1.0 Sep 2010 Preliminary Short Data Sheet

FEATURES SUMMARY
Ethernet MAC

Provide up to 4 MAC Controllers for Gigabit and Fast Ethernet framing and auto-negotiation in compliant with IEEE 802.3 Support port-based flow control as 802.3x. The received flow control frame from Ethernet line is bypassed/discarded to SONET transparently Rate limiting based Rx Ethernet FIFO Jumbo frame support up to 9Kbyte MAC Counters for Ethernet Statistics as RFC2819 Optional FCS Insertion at Transmit Ethernet MAC Ethernet serial loop back out and/or parallel loop back in for diagnostic Support 1K MAC address table Automatic SA based learning using Hash function Automatic Aging. Aging enable/disable by microprocessor Forwarding packet to SONET/SDH based on MAC DA Support up to 8 collision MAC address per Hash key Support multicast/broadcast for MAC learning only Support MAC filter for remote loop back applications Provide up to 504 queues for data packet Support performance counters per queue as RFC2819

SONET/SDH

Built-in 2 OC-12/STM-4 Framers Full SONET/SDH Section/Line Overhead processing Hardware based APS processing for Linear and UPSR Full Hi-order and Lo-order Path monitoring/termination Full SONET/SDH Line 10-3 to 10-9 hardware BER detection Full Hi-order and Lo-order with 10-3 to 10-9 hardware BER detection

MAC-Learning & Management

STS/AU/VT/TU Cross Connect

Full non-blocking Cross-connect for STS-1/VC-3/VT/TU Integrates 252 E1 framers source from VT/TU Map/DeMap Provide unframe, basic and CRC-4 framing mode Provide full error, alarm and performance counters for E1 maintenance Implements bit asynchronous mapping of 252 E1 to VT2/TU12 Asynchronous E1 to VT/TU Map with Jitter Attenuation Extraction/Insertion Sa bits for Data Link processor Support local line loop back and remote line loop back for diagnostic

PDH Features

Data Encapsulation

PPP/HDLC/LAPS and GFP simultaneously, full-duplex 252 channels PPP/HDLC/LAPS and GFP mapping to E1 in compliance with G.8040, RFC1638, X.86 Complies with ITU-T G.7041 (GFP), RFC-1619/1662/2615 (PPP), ITU-T X.86 (LAPS) mapping standards Core HEC and packet FCS checker/generator and 1-bit Core HEC error correction Aborted sequence detection/generation Packet Payload scrambling/de-scrambling Bit stuffing and byte stuffing on PPP Supports rate adaptation for LAPS/PPP Extraction and insertion header field support Supports frame extraction and Insertion

System Clock Synthesizer

Accepts the multiple of 8KHz input reference clock and monitor clock Accepts an 8KHz or 1.544MHz/2.048MHz input reference clock and an 8KHz or 1.544MHz/2.048MHz input monitored clock Selectable clock reference and clock monitoring from SONET/SDH Line or Hi-order or Lo-order path Supports Free-run, Locked, and Holdover modes of operation Supports working/protection clock synchronization with multiframe phase accuracy of 6.43ns 256 standard HDLC channels E1 FDL from PDH framers DCC bytes from SONET/SDH framers Bit-oriented Message and Facility Data Link from PDH framers Flexible datalink buffer setup and management significantly offloading host processor from real time demands from the large channel count

Datalink Controller

Please contact sales@arrivetechnologies.com for further information

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