A Digital Instantaneous Frequency

Measurement Technique Utilising

High-Speed ADCs and FPGAs
2006 CSIR Research and Innovation Conference
CSIR Defence, Peace, Safety and Security
Dr PL Herselman
Visiting Researcher at the University College London
27 February 2006
Slide 2 CSIR 2006 www.csir.co.za
Electronic Warfare
Image courtesy of Altera, www.altera.com
Slide 3 CSIR 2006 www.csir.co.za
Signal Intelligence (SIGINT)
Complex battlefield multiple RF emitters
Receiver analyses intercepted waveforms
Situational awareness
Queuing of defensive/evasive action(s)
Compact packaging for operational systems
Employed on a range of systems
Airborne Warning and Control System (AWACS)
Image courtesy of Rockwell Collins
Movie courtesy of Macom
Image courtesy of NATO, www.nato.int
Image courtesy of
Northrop Grumman
Slide 4 CSIR 2006 www.csir.co.za
Agenda
Background
DIFM research as part of CSIR
Defence, Peace, Safety and
Security R&D strategy
IFM Theory
Overview of basic theory
Optimal Time Delay
Led to DIFM invention
DIFM Basics
Digital implementation of IFM
using innovative parallel DSP
techniques
Example Implementation
Shared aperture DIFM on
SWIFT500 DRFM system
Simulation Results
Bit-true functional simulations for
a range of input signals
Experimental Verification
Results of a prototype system
Conclusions
Background
Slide 6 CSIR 2006 www.csir.co.za
Digital Radio Frequency Memory (DRFM)
Research and Development at the CSIR
Active R&D field since 1999
Advanced and highly configurable repeater
Analog to digital converter memory digital to analog converter
Information bandwidth limited to half the sampling rate
Utilised in a range of applications
Field (electronic countermeasures)
Obscure the platform (e.g aircraft)
Deceive the hostile radar
Laboratory (test equipment)
Coherently simulate the signals emitted by electronic
countermeasures and the signals reflected from targets
Slide 7 CSIR 2006 www.csir.co.za
Digital Radio Frequency Memory (DRFM)
Research and Development at the CSIR
Levels of development
Digital DRFM Module
DRFM Kernel
DRFM-based simulator system
Slide 8 CSIR 2006 www.csir.co.za
Need for Frequency Measurement
in DRFM-Based Systems
Pulse qualification
Deceive and obscure only hostile systems
Frequency dependant techniques
Accurate Doppler response
RF bandwidth is a scarce resource
Maximise ECM effectiveness
Compensate DRFM-induced phase
perturbations
Poster presentation
Estimate
required in
less than a
microsecond
Slide 9 CSIR 2006 www.csir.co.za
Frequency Measurement Solutions
Instantaneous Frequency
Measurement (IFM)
Analog technique
Combined with analog-to-digital
converter DFD
Multiple parallel IFMs
Single output
Dual aperture
Discrete Fourier Transform
(DFT)
Measures spectral response
Aliased to [0,f
s
/2) frequency
range
Multiple input signals
Multiple outputs
Preferred frequency
estimation technique
Graph courtesy of Altera Table taken from Schleher (1986)
Instantaneous Frequency
Measurement Theory
Slide 11 CSIR 2006 www.csir.co.za
Instantaneous Frequency Measurement
Digital Frequency Discriminator
Analog
Input
R
L
I
Low-pass
Filter
ADC
c
0
*arccos[c
1
*y
filt
(t
n
)]
y
filt
(t
n
) f
0
(t
n
)
Digital
Output
Mixer
3 dB
Coupler
Analog
Delay line
Lookup Table
Multiply signal with delayed replica
Low-pass filter
Inverse cosine operation
Typically preceded with ADC
Lookup table
Digital Frequency Discriminator (DFD)
( ) ( ) ( ) [ ]
0 0 0
2
0
2 4 cos 2 cos
8
f t f f
A
t y
mix
+ =
( ) ( ) ( ) ( ) ( ) 0 2 , 2 cos 0
8
0 0
2
0
H f H f H
A
t y
filt
<<
( )
( )
(

0
8
arccos
2
1
2
0
0
H A
t y
f
filt

Optimal Time Delay

Slide 13 CSIR 2006 www.csir.co.za
Delay Line Calculation
One-to-one mapping: Input frequency output value
Maximum one-to-one input frequency calculated as
Inverse of twice the maximum input frequency
IFM with frequency range equal to ADC IBW
Unambiguous input frequency range [0,f
s
/2) chosen
Optimal time delay = one ADC sampling period
( )
( )
( )
( )
( )
0 ,
2
1
2 1
2
1
1 arccos
2
1
max 0 max 0 max 0
= = + = = n
f
n
f f

( )
s
s
s
t
f
f
f
= =
|

\
|
= =
1
2
2
1
2
1
max 0

Digital Instantaneous Frequency

Measurement Basics
Slide 15 CSIR 2006 www.csir.co.za
Steps 1&2: Sampling, Quantisation and
Multiplication
Sampling and quantisation
Multiplication with time-delayed replica
( ) ( ) [ ] ( ) [ ]
( ) ( ) ( ) n n F
D
A
n F
D
A
round
f
f
F n F A Q n
f
f
A Q nt y Q n y
q
N N
s s
s q


+ =
(

=
= =
(

|
|

\
|
= =

0
0
0
1
0
0
0 0 0
0
0
2 cos 2 2 cos 2
2
, 2 cos 2 cos
( ) ( ) ( )
( ) ( ) [ ]
( ) ( ) ( ) [ ] ( ) { } ( ) ( ) 1 1 2 cos 1 2 cos 2
2 4 cos 2 cos 2
1
0 0
0
0 0 0
1 2
2
2
0
+ + +
+ =
=

n n n n F n n F
D
A
F n F F
D
A
n y n y n y
q q q q
N
N
q q mix


Slide 16 CSIR 2006 www.csir.co.za
Step 3: Low-Pass Filtering
Finite Impulse Response (FIR) digital filter
where
( ) ( )
( ) ( ) ( ) ( ) ( ) [ ] ( ) 2 2 cos 2 cos 0 2
0 0 0 0 0
1 2
2
2
0
0
n F H F n F F H F H
D
A
k n y c n y
q LPF LPF LPF
N
N
k
mix k filt


+

+

+ =
=

4
, 2 1
4
, 2
0 0 0
0 0 0
s
s
f
f F F
f
f F F
> =

Slide 17 CSIR 2006 www.csir.co.za

Step 3: Low-Pass Filtering
Interactive filter design tools (e.g. MATLAB FDATool)
Slide 18 CSIR 2006 www.csir.co.za
Step 4: Inverse Cosine Operation
Digital inverse cosine estimation
Cordic algorithm
Lookup table
Output of low-pass filter is used as the input to a lookup table
Lookup table output estimates frequency of the input signal
( )
( )
( )
|
|

\
|

0 2
arccos
2
1 2
1 2 2
0
2
LPF
N
filt
N
out
H A
D n y
n y
out

Slide 19 CSIR 2006 www.csir.co.za

Digital Instantaneous Frequency
Measurement
Advantages
Mixing product relatively linear
yielding lower spurious response
Filter response can be optimised
for the specific requirements, i.e.
fast response versus
measurement accuracy
Issues
FPGA clock speeds > 100 MHz
DIFM up to 50 MHz bandwidth
with serial processing
Exhibit the same amplitude
sensitivity as an analog IFM
Slide 20 CSIR 2006 www.csir.co.za
Parallel Processing DIFM
High-speed flash converter ADCs
> 10 bits
> 2 GSPS
Techniques often employed include time-domain
demultiplexing, i.e. wider bus, lower data rate
ASIC or commercial demultiplexers
For 1.2 GSPS 10-bit ADC
16x demulitplex
75 MSPS 160-bit
Calculate in a single FPGA clock cycle
15 multiplications
14
th
order FIR filter
Possible to artificially extend the bus width
Slide 21 CSIR 2006 www.csir.co.za
Amplitude Insensitive DIFM
Suppose an estimate of the input amplitude was available
Technique analogous to DIFM with time delay equal to 0
Multiply
Low-pass
( )
( )
( )
( )
( ) [ ]
( )
( )
( ) ( ) ( ) ( ) ( ) [ ]
( )
2
0
0 0 0 0 0
1 2
2
0
2
0
2
0
2
2 2 cos 2 cos 0 2
4
,
A
n
F H F n F F H F H
D
n A
A
n y
n A
n y
n A
n y
n y
q
LPF LPF LPF
N
a
filt
a
filt filt
div

+

+
>>
+
= =

( ) ( ) ( ) ( ) ( ) ( ) n y 0
2
q
= = =

n y n y n y n y n y
q q q q mix
( ) ( ) ( ) ( ) ( ) [ ] ( ) n F H n F F H H
D
A
n y
q LPF LPF LPF
N
filt
+ + + =

0 0 0
1 2
2
2
0
2 cos 0 2
Slide 22 CSIR 2006 www.csir.co.za
Amplitude Insensitive DIFM
Divide basic DIFM filter output with amplitude estimation
Inverse cosine lookup table yield frequency estimation
Advantages
Amplitude estimation exactly aligned with frequency estimation
No external calibration or alignment required
Time-domain multiplex hardware
( ) ( )
( )
( )
( ) ( ) ( )
( )
0
0 0 0
0
0
2 cos
2 2 cos
0
2 cos
F
n F H F n F
H
F H
F n y
q LPF
LPF
LPF
div

+
( )
s
lt
f
f
F n y
0
0
2 2 =
Example Implementation
Slide 24 CSIR 2006 www.csir.co.za
SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
1.2 GSPS , 500 MHz IBW
16x demultiplexing
Stratix 1S30 with 96 9x9 multipliers
Slide 25 CSIR 2006 www.csir.co.za
SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
y
q
(n)
y
q
(n-1)
y
q
(n-15)
y
q
(n-2)
InputCast0
InputCast1
InputCast2
InputCast15
UnitDelay0
UnitDelay1
UnitDelay2
UnitDelay15
UnitDelay16
UnitDelay17
UnitDelay18
UnitDelay24
y'
q
(n-32)
y'
q
(n-33)
y'
q
(n-40)
y'
q
(n-31)
y'
q
(n-18)
y'
q
(n-17)
y'
q
(n-16)
y'
q
(n-2)
y'
q
(n-1)
y'
q
(n)
y'
q
(n-15)
U
n
i
t
D
e
l
a
y
8
MuxMult24
14
c
0
22
c
1
38
c
2
57
c
3
81
c
4
109
c
5
138
c
6
168
c
7
196
c
8
221
c
9
240
c
10
252
c
11
255
c
12
252
c
13
240
c
14
221
c
15
196
c
16
168
c
17
138
c
18
109
c
19
81
c
20
57
c
21
38
c
22
22
c
23
14
c
24
y
' q
(
n
-
2
4
)
y
'
q
(
n
-
2
5
)
Flip-Flop
MuxMult1
MuxMult0
Adder
DeMux1
Select
0 1
DeMux2
Select
0 1
UnitDelay25
UnitDelay26
Inverse
Lookup
Table
Multiply
Arccos
Lookup
Table
y
out
y
1mm
y
2mm
y
24mm
y
a
UnitDelay25
y
dm1
y
dm2
y
m
Mux#A
Mux#B
Select
0
1
Select
0
1 y'
q
(n-#)
y'
q
(n-#-1)
y'
q
(n-#-16)
Select In
Multiply
#A
Multiply
#B
Coeff In #
Y
#mm
(m+d
1
)
Slide 26 CSIR 2006 www.csir.co.za
SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
Key specifications
9-bit multiplication
24th order low-pass FIR filter with Chebyshev windowing
Cut-off frequency of 100 MHz and 48 dB side-lobe suppression
Frequency response 50 MHz to 550 MHz
Time-multiplexed resources to estimate amplitude and frequency
Division implemented in a two-step process
Inversion of denominator using lookup table (12-bit x 12-bit)
Multiplication of numerator with inversed denominator
12-bit by 10-bit inverse cosine lookup table
Simulation Results
Slide 28 CSIR 2006 www.csir.co.za
Monochromatic Input Signal With Additive
Coloured Noise
Slide 29 CSIR 2006 www.csir.co.za
Analysis of DIFM Accuracy
Slide 30 CSIR 2006 www.csir.co.za
Key Performance Specifications
High signal-to-noise ratios
Mean deviation less than 2 MHz
Absolute error less than 6 MHz across bandwidth
Absolute error less than 2 MHz in > 300 MHz bandwidth
RMS error less than 3 MHz across bandwidth
RMS error less than 1 MHz in > 300 MHz bandwidth
Low signal-to-noise ratios
Bias in frequency estimation
Due to bias in amplitude estimation
Reduced by implementing higher order FIR filter (longer latency)
Latency (processing time)
13 FGPA clock cycles (173.33 ns)
Throughput rate
2 FGPA clock cycles (37.5 MHz)
Experimental Verification
Slide 32 CSIR 2006 www.csir.co.za
Quantitative Laboratory Experiments
Conclusions
Slide 34 CSIR 2006 www.csir.co.za
Conclusions
Viable, shared aperture, frequency estimation technique
Implemented efficiently in current commercial hardware
Results comparable to existing analog techniques
Flexibility and ability to be optimised for the specific
requirements
Real-time changing the filter coefficients
Insensitive to temperature
Does not require periodic calibration to maintain accuracy
Operationally superior to its analog counterparts
South African provisional patent application 2006/00946,
2006-02-01