DAYALBAGH EDUCATIONAL INSTITUTE Faculty of Engineering

ESHAN SHAILENDRA Bsc(Engg.) 3rd year Roll No.- 094012 TERM PAPER TOPIC :- CMOS Op-Amps Course :- Basic Electronics Design (EEM 511)

CONTENTS
I. II. III. IV. V. VI. Introduction; Operational Amplifiers: Stages in a CMOS Op-Amp viz differential transconductance stage, intermediate stage, output/inverting stage. Categorization of CMOS op amps: 2 stage op amps, Cascoded op amps, Folded cascade op amps; Compensation techniques: Miller compensation, RHP zero controlling, Feed-Forward compensation; Generalized Design of CMOS op amps : Detailed designing procedure for Two stage Op-Amp. References

Note:
The paper presents a basic overview on CMOS Op Amps including various stages, categories, compensation techniques etc, giving an emphasis on two stage op amp (rather than cascaded one).Furthermore detailed modeling and simulation is complex process and is done using computer analysis (using PSPICE, SIMULINK, MODELSIM etc). Analysis using these software is beyond the scope of this paper.

The operational amplifiers have become one of the most versatile and important building block in analog circuit design. They are basically voltage controlled voltage sources (VCVS) having sufficiently high forward gain with zero input and output impedances. CMOS op amps are very popular nowadays due to increasing need of mixed analog and digital signal chip compatibility. As CMOS is already popular in digital circuits due to their high densities and low power dissipation, their use in analog interface circuits also increases. They are similar in architecture to their bipolar counterparts. A block diagram of general two stage op amp is shown: Differential transconductance stage forms input of op amp normally providing a good portion of overall gain. It involves a differential amplifier, designed to produce a high input impedance, large CMRR, and PSRR, low offset voltage, low noise and high gain. Its output should preferably be single ended so that rest of the op amp need not contain symmetric differential stages. Second stage is typically an inverter for enhancing gain achieved in first stage. The second block may perform a variety of functions, ranging from level shifting, providing additional gain, differential to single ended conversion etc. If a low resistance load is to be driven, second stage must be followed by a Buffer stage for lowering output resistance and maintaining large signal swing to drive large output current. Compensation is needed to achieve a stable closed loop performance. . Transconductance amplifier stage Inverters generally used in second stage use common source configuration with either an active resistor for a load, or a current sink/source as a load resistor. These inverters can be active load inverter (low gain but highly predictable low/high signal charecterstics),

current source inverter (higher gain)and push-pull inverters (highest gain) etc.

CATEGORISATION OF OP-AMPS
Amplifiers generally consist of a cascade of voltage to current and current to voltage converting stages. A voltage to current stage is known as transconductance stage and a current to voltage stage known as the load stage. Based on this categorization, we derive two major op amp architectures. The first is a Two stage op amp and the second is Folded cascoded Op Amp.

Two stage Op-Amps

It consists of a cascade of V to I and I toV stages. The first stage consists of a differential amplifier converting the differential input voltages to differential currents. These differential currents are applied to a current mirror load recovering the differential voltage.

This is achieved through a differential voltage amplifier. The second stage consists of a common source MOSFET converting the second stage input voltages to current. This FET is loaded by a current sink load, which converts the current to voltage at the output. This is achieved through a current sink inverter.

Schematic of a Two stage operational amplifier

Cascode Op-Amps
It follows an architecture which aims to improve the common mode gain and power supply rejection of the two stage op amp. It can be considered as a cascade of a differential transconductance stage with a current stage followed by a cascade current mirror load. An important trait of folded cascade op amp is that it has a push pull output, ie. Op amp can actively sink or source current from the load. In case of two stage op amps, sinking or sourcing capability is fixed.
Schematic of a Folded cascode operational amplifier

ANALYSIS AND COMPENSATION OF TWO STAGE CMOS OP-AMPS

Any Op amp needs to be compensated before it is to be used in a closed loop configuration. Its of primary importance that the signal fed back to the input of the Op amp be of such amplitude and phase that it doesnt continue to regenerate itself around the loop. Should this occur, the output of amplifier would be either be clamped at one of the supply potentials (regeneration of DC) or oscillation (regeneration at some frequency other than DC). To avoid the situation, compensation becomes necessary.

Let A(s) be the open loop amplifier voltage gain, F(s) be transfer function for external feedback, so Loop gain L(s) = -A(s)F(s) To avoid clamping or oscillations in output, we enforce a condition stated as: Arg[-A(j)F(j)] = Arg[L(j)] >0o , { where = |A(j)F(j)| = |L(j)| = 1 }

If the condition is met, the feedback system is said to be stable (ie. Sustained oscillations cant occur). The relationship can be understood with the help of following Bode Plot showing response of Arg[-A(j)F(j)] and |A(j)F(j)| versus frequency.. The requirement for stability is that |A(j)F(j)| crosses the 0dB point before plot of Arg[-A(j)F(j)] reaches 0o. A measure of stability is provided by the value of phase when |A(j)F(j)| is 0dB, known as phase margin m, where phase margin is m= Arg[-A(j)F(j)] = Arg[L(j)] The importance of adequate phase margin is understood with the help of figure alongside showing time response of a closed loop system in time domain. Hence we conclude that larger phase margin results in less ringing of the output signal. In most situations, a phase margin of about 60o(atleast 45o) is preferable. Now consider the second order, small signal model for an uncompensated op amp. The locations for the two poles are given by the following equations : PStageI = -1/(RICI) PStageII = -1/(RIICII) where RI, CI, RII, CII are resistances from ground seen from the output of Ist and IInd stage respectively. Now for worst case stability, F(s)=1 and phase margin is significanyly less than 45o which means that op amp should be compensated before using it in closed loop configuration.
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Miller compensation
Miller compensation is one of the widely used methods for compensating a CMOS op amp. This technique involves connecting a capacitor from output to the input of secondary transconductance stage gmII as illustrated in figure. Due to addition of capacitance, shunting resistance RI is increased by an additive amount of gmIIRIICc. This moves pole pI to pI closer to origin of complex frequency plane, by an amount depending on the second stage gain. Second pole p2is moved to p2, ie. away from origin, resulting from a negative feedback reducing the output resistance of the second stage [fig, on next page] as derived below. Overall transfer function resulting from addition of Cc is:

( ) ( )

( , ( )

)(

)(

)( -

)( ,

) -

Now expressions for poles are: If CII is much greater than CI and Cc is greater than CII, then expression for p2 can be approximated by,

, Furthermore a zero occurs on positive real axis due to .

The figure shows results of compensation illustrated by an asymptotic magnitude and phase plot. Here the second pole doesnt begin to effect the magnitude until is less than unity. The RHP zero increases the phase shift (acts like LHP pole) but increases the magnitude (acts like LHP zero). Hence if either zero or pole move towards origin, the phase margin will be degraded. So, the task of compensating an amplifier for closed loop application is to move all poles and zeroes except for the
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feed forward path through Cc , located at

The figure above illustrates movement of poles from their uncompensated to their compensated positions.

dominant pole (pI) sufficiently away from the origin of the complex frequency plane (beyond unity gain bandwidth of frequency) to result in a phase shift as depicted by the figure above.

Now, we shall concentrate on two most dominant poles and the RHP zero out of many poles generated by parasitic capacitances as depicted in the figure of actual two stage op amp . PI = Dominant left half pole or the Miller Pole =
( )( )

PII = Left half plane output pole . =

ZI = RHP zero
Two stage Op Amp with parasitic and circuit stage capacitances

GB =

The above stated three roots influence the dynamic performance of Op Amp. The miller pole is obtained as a result of compensating capacitor Cc. To obtain expression for PI, , Cc is multiplied by gain of second stage gIIRII to give capacitor in parallel with RI of gIIRIIC. Multiplying this capacitor times RI gives expression for PI . Magnitude of second root PII must be atleast equal to GB and is due to capacitance at output of Op Amp. Its obtained by multiplying small signal resistance of MOS diode 1/gm by CII and inverting. The third root, RHP zero is highly undesirable root because it boosts the loop gain magnitude while causing loop phase shift to become more negative. Both these factors reduce stability of the system. This root comes from the fact that there are two signal paths from input to output. One path is from gate of M6 through compensating capacitor Cc to Vout . . Other path is from transistor M6 to output Vout . At some complex frequency, signal through both these paths become equal and opposite creating a zero. For an op amp model with two poles and one RHP zero, zero is kept ten times higher than GB, and the 2nd pole is placed 1.22 times higher than GB for a 45o phase margin in order to satisfy the condition: m= 180o- Arg[A(j)F(j)] = 180o- tan-1(/|P1|) - tan-1(/|P2|) - tan-1(/|Z1|) =45o Assuming unity gain is GB, we replace by GB, giving

180o- tan-1(GB/|P1|) - tan-1(GB/|P2|) - tan-1(GB/|Z1|) = 45o

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 180 - tan (AV(0)) - tan (GB/|P2|) - tan (0.1) = 45 Expressing in mathematical terms: Condn. 1 Condn. 2 ZI > 10GB |PII| > 1.22GB

-1

-1

-1

Combining these two equations, we obtain value of Cc as Cc = 0.122C2

Controlling the right half plane zero

The RHP zero tends to limit the GB that might otherwise be achievable if it werent present. There are several ways to eliminate this zero. First approach discussed here is to eliminate the feedforward path by placing a unity gain buffer in the feedback path of compensating capacitor. The technique is illustrated in the figure below.

Transfer function for small signal model depicted is:

( ) ( )

( ,

)(

)(

)( -

) , ( )-

Roots of this equation are: PI = PII = Hereby we should note that the poles of circuit have approximately

remained the same, but the zeroes have been removed. The above analysis neglects the output resistance of buffer amplifier Ro, which can be significant. Taking output resistance into account and assuming thatits less than RI or RII results in an additional pole p4 and LHP zero Z2 given by:

P4 =

)-

; Z2 =

Although the LHP zero can be used for compensation, the additional pole makes this method less desirable than the method of inserting a nulling resistor in series with Cc . The circuit configuration for nulling resistor method is shown below.

The circuit shown has following node voltage equations:

. .
The equations can be solved to give

/( /(
( ) ( ) *

) ; )
,( ) -+

a = gmIgmIIRIRII ; d = RzRIRIICICcCII ; b = (CII+Cc)RII + (CI+Cc)RI + gmIIRIRIICc +RzCc ( ) ( [

)]

Now if Rz is assumed to be less than RI and RII and the poles are widely spaced, then roots of above stated equation can be approximated as
)

; p4 =

and RHP zero is z1

To view how nulling resistor accomplishes control over RHP zero we break output stage into 2 parts as depicted by figure, such that
. / . /

The resistor Rz allows independent control over the placement of zero. In order to remove the RHP zero, Rz must be set equal to 1/gmII . Another approach (not discussed here) is to move zero from RHP to LHP and place it on top of pII. As a result, pole associated with output loading capacitance is canceled.
Illustration of how nulling resistance accomplishes control of RHP zero.
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Feedforward compensation
Another compensation technique used in CMOS op amps is the feedforward scheme shown in figure a. In this circuit, the buffer is used to break the bidirectional path through the compensating capacitor. Unfortunately, this circuit results in a zero that is in right half plane. If either the polarity of the buffer or the high gain amplifier is reversed, the zero will be in left half plane. Figure b shows a feedforward compensation technique that has a zero in the left half plane because the gain of buffer is inverted. Figure c can be used as a model of the circuit. The voltage transfer function can be obtained as

( ) ( )

( ( )( ( (

) )
In order to use the circuit to achieve compensation, its necessary to place the zero located at gmII/ACc above the value of GB so that boosting of the magnitude will not negate the desired effect of positive phase shift caused by zero.

(a) Feedforward resulting in a RHP zero; (b) Feedforward resulting in an LHP zero; (c) Small signal model for (b)

Fortunately, the phase effect extends over a much larger frequency range than the magnitude effects so that this method will contribute additional phase margin to that provided by the feedback compensation technique. Another form of feedforward compensation is to provide a feedforward path around a non inverting amplifier as shown in figure d. This type of compensation is also used in source followers, where a capacitor is connected from gate to source of the source follower. The capacitor will provide a path that bypass a transistor at high frequencies.

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DESIGN OF A CMOS OPERATIONAL AMPLIFIER

The design of an Op-Amp can be performed in two different stages independent of each other. These are:(i) Deciding the basic structure of the Op-Amp and selecting DC currents, sizing the transistors and (ii) Designing the compensation circuit. The table alongside is useful for guiding the CMOS OpAmp design process. However, type of compensation used also influences the design of each block, particularly compensation, which can be either feed forward or feed backward depending on the type of characteristics desired, number of stages used etc.

Designing a two stage Op-Amp

Now having discussed the general classification, fundamental building blocks, compensation, and general approaches to op-amp design and compensation, we proceed to develop a procedure that will enable a first cut design of two stage op amp. Before beginning the task, important relationships describing op-amp performance will be summarized. Assuming that gmI = gmII, gm6 = gmII,

.
Skew rate =

gds2+ gdsII = GI and gds6+ gdsI = GII

; First stage gain Av1 =

( )

; ; Gain bandwidth GB = (gmI / Cc);

Second stage gain Av2 = Output pole p2 =

; RHP zero zI =

;
|VT03|(max) + VT!(min) ;

Positive CMR Vin(max) = VDD

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Negative CMR Vin(min) = VSS Saturation voltage Vds(sat) =

|VT1|(max) + VDS5(sat) ; ;

For deriving above relationships, its assumed that all transistors are in saturation. The following design procedure assumes that specifications for the following parameters are given:a) b) c) d) e) f) g) Gain at DC, AV(0), Gain Bandwidth, GB, Input common-mode range, ICMR, Load capacitance, CL Slew rate, SR Output voltage swing, Power dissipation, Pdiss

The design procedure begins by choosing a device length to be used throughout the circuit. This value will determine the value of the channel length modulation parameter , which will be a necessary parameter in the calculation of amplifier gain. Having chosen the nominal transistor device length, one next establishes the minimum value for the compensation capacitor Cc it was shown previously that placing the output pole P2 2.2 times higher then the GB permitted a 600 phase margin assuming that the RHP zero z1 is placed at or beyond ten times GB. It was shown in previous equations that such pole and zero placements result in the following requirement for the minimum value for Cc. should fulfill the condition: Cc > (2.2/10) CL Next, determine the minimum value for the tail current I5, based on slew-rate requirements. The value for I5 is determined to be equal to SR(Cc). If the slew-rate specification is not given, then one can choose a value based on settling-time requirements. Next determine a value that is roughly ten times faster than the settling-time specification, assuming that the output slews approximately one-half of the supply rail. The value of I5 resulting from this calculation can be changed later if need be. The aspect ratio of M3 can now be determined by using the requirement for positive input common-mode range. The following design equation for (W/L)3 was derived from previous equations. ( ) ( ), ( ) | |( ) ( )-

If the value determined for (W/L)3 is less than one, then it should be increased to a value that minimizes the product of W and L. This minimizes the area of the gate region, which in turn

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reduces the gate capacitance. This gate capacitance contributes to the mirror pole which may cause degradation in phase margin. Requirements for the transconductance of the input transistors can be determined from knowledge of Cc and GB. The transconductance gml can be calculated using the equation, gml = GB (Cc) The aspect ratio (W/L)1 is directly obtainable from gml as shown below:

( )

)( )

Enough information is now available to calculate the saturation voltage of transistor M5. Using the negative ICMR equation, we calculate Vds5 using the following relationship derived from previous equations.

. /

If the value for Vds5 is less than about 100 mV, then the possibility of a rather large (W/L)5 may result. This may not be acceptable. If the value for Vds5 is less than zero, then the ICMR specification may be too stringent. To solve this problem, I5 can be reduced or (W/L)1 increased. The effects of these changes must be accounted for in previous design steps. One must iterate until the desired result is achieved. With Vds5 determined, (W/L)5 can be extracted using previous equations in the following way:

( )

)(

At this point, the design of the first stage of the op amp is complete. We next consider the output stage. For a phase margin of 600, the location of the output pole was assumed to be placed at 2.2 times GB. Based on this assumption and the relationship for |p2| in Eq. (6.3-5), the transconductance gm6 can be determined using the relationship: gm6 = 2.2(gm2)(CI / C2) Generally, for reasonable phase margin, the value of gm6 is approximate ten times the input stage transconductance gm1. At this point, there are two possible approaches to completing the design of M6. The first is to achieve proper mirroring of the first stage current mirror load of fig. 6.3-1 (M3 and M4). This requires that Vsg4 = Vsg6. Using the formula for gm, which is KS(VgsVt ), we can write that if Vsg4 = Vsg6, then:

Knowing gm6 and S6 will define the dc current I6 using the following equation:
( )( ) ) ( )( )

One must now check to make sure that maximum output voltage specification is satisfied. If this is not true, then the current or W/L ratio can be increased to achieve a smaller Vds (sat). If
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these changes are made to satisfy the maximum output voltage specification, then the proper current mirroring of M3 and M4 is no longer guaranteed. The second approach to designing to output stage is to use the value of gmb and the required Vds (sat) of M6 to find the current. Combining the defining equation for gmb and Vds (sat) result in an equation relating W/L, Vds(sat), gmb and process parameters. Using the relationship, S6 = (W/L)6 =
( )

with the Vds(sat) requirement taken from the output

range specification one can determine (W/L)6. Above equation for I6 is used as before to determine a value for I6. In either approach to finding I6 one also should check the power dissipation requirements since I6 will most likely determine the majority of the power dissipation. The device size of M7 can be determined from the balanced equation given below: S = (W/L) = (W/L)5(I6/I5) = S5(I6/I5) The first cut design of all W/L ratios is now complete. Figure below illustrates the above design procedure showing the various design relationship and where they apply in the two stages CMOS op amp. At this point in the design procedure, the total amplifier gain must be checked against the specifications. Now gain
( ( )( ) ( ) )

If the gain is too low, a number of things can be adjusted. The best way to do this is to use table given below, which shows the effects of various device sizes and current on the different parameters generally specified. Each adjustment may require another pass through this design is procedure in order to ensure that all specifications have been met.

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References I. II. III. IV. Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford University Press. Roubik Gregorian, Introduction to CMOS op-amps and comparators. D. De Vento, Powerpoint slides on CMOS op-amps,07/10/2006. Internet.

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