ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

Lecture 1: Introduction

Sam Palermo Analog & Mixed-Signal Center Texas A&M University

Class Topics
System and design issues relevant to high-speed electrical (and optical) signaling Channel properties
Modeling, measurements, communication techniques

High-Speed link circuits

Drivers, receivers, equalizers, timing systems

Link system design

Modeling and performance metrics

Link system examples

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Administrative
Instructor:
Sam Palermo 315E WERC Bldg., 845-4114, spalermo@ece.tamu.edu Office hours: TR 9:00am-10:30pm

Lectures: MW 5:45pm-7:00am, ZACH 223A Lab: R 4:00pm-5:50pm, ZACH 203

Lab begins second week

Class web page

http://www.ece.tamu.edu/~spalermo/ecen689.html

Class Material
Textbook: Class Notes and Technical Papers Key References
Digital Systems Engineering, W. Dally and J. Poulton, Cambridge University Press, 1998. Advanced Signal Integrity for High-Speed Digital Designs, S. H. Hall and H. L. Heck, John Wiley & Sons, 2009. High-Speed Digital Design: A Handbook of Black Magic, H. Johnson & M. Graham, Prentice Hall, 1993. Design of Integrated Circuits for Optical Communications, B. Razavi, McGraw-Hill, 2003.

Class notes
Will hand out hard copies in class
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Grading
Exams (50%)
Two midterm exams (25% each)

Homework & Labs (25%)

Labs (Prelab + Report) and homeworks weighted equally Collaboration is allowed, but independent simulations and write-ups Need to setup CADENCE simulation environment Due at beginning of class No late homework will be graded

Final Project (25%)

Groups of 1-2 students Report and PowerPoint presentation required

Prerequisites
This is a circuits AND systems class Circuits
ECEN474 or approval of instructor Basic knowledge of CMOS gates, flops, etc Circuit simulation experience (HSPICE, Spectre)

Systems
Basic knowledge of s- and z-transforms Basic digital communication knowledge MATLAB experience
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Simulation Tools
Matlab Stateye (Statistical BER link analysis) Cadence 90nm CMOS device models
Can use other technology models if they are a 90nm or more advanced CMOS node

Other tools, schematic, layout, etc are optional

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Desktop Computer I/O Architecture

Many high-speed I/O interfaces Key bandwidth bottleneck points are memory (FSB) and graphics interfaces (PCIe) Near-term architectures
Integrated memory controller with serial I/O (>5Gb/s) to memory Increasing PCIe from 2.5Gb/s (Gen1) to 8Gb/s (Gen3)

Other serial I/O systems Multi-processor systems Routers

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Serial Link Applications

Processor-to-memory
RDRAM (1.6Gbps), XDR DRAM (7.2Gbps), XDR2 DRAM (12.8Gbps)

Processor-to-peripheral
PCIe (2.5, 5, 8Gbps), Infiniband (10Gbps), USB3 (4.8Gbps)

Processor-to-processor
Intel QPI (6.4Gbps), AMD Hypertransport (6.4Gbps)

Storage
SATA (6Gbps), Fibre Channel (20Gbps)

Networks
LAN: Ethernet (1, 10Gbps) WAN: SONET (2.5, 10, 40Gbps) Backplane Routers: (2.5 12.5Gbps)
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Chip-to-Chip Signaling Trends

Lumped capacitance

Decade
1980s

Speeds
>10Mb/s >100Mb/s

Transceiver Features
Inverter out, inverter in Termination Source-synchronous clk. Pt-to-pt serial streams Pre-emphasis equalization Adaptive Equalization, Advanced low power clk. Alternate channel materials

Transmission line

Lossy transmission line

1990s

2000s

>1 Gb/s

Channel Transmit Filter h(t)

noise

Future
Sampler RX Equalizer CDR

>10 Gb/s
Slicer

Slide Courtesy of Frank OMahony & Brian Casper, Intel

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Increasing I/O Bandwidth Demand

Single Multi Many-Core Processors Tera-scale many-core processors will aggressively drive aggregate I/O rates
ITRS Projections* 80 processor cores On-die mesh interconnect network w/ >2Tb/s aggregate bandwidth 100 million transistors 275mm2

Intel Teraflop Research Chip

S. Vangal et al, An 80-Tile Sub-100W TeraFLOPS Processor in 65nm CMOS," JSSC, 2008.

*2006 International Technology Roadmap for Semiconductors

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High-Speed Electrical Link System

Channel TX RX

TX data

Deserializer

Serializer

RX data

ref clk

PLL

TX clk TX data TX clk RX clk

RX clk

CDR

D[n]

D[n+1]

D[n+2]

D[n+3]

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Electrical Backplane Channel

Chip package (crosstalk) Package via (reflections)

Line card trace (dispersion)

On-chip termination (reflections) Backplane connector (crosstalk)

Backplane trace (dispersion) Line card via (reflections)

Backplane via (major reflections)

Frequency dependent loss

Dispersion & reflections

Co-channel interference
Far-end (FEXT) & near-end (NEXT) crosstalk
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Channel Performance Impact

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Channel Performance Impact

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Backplane Link Example

A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology

Mounir Meghelli, Sergey Rylov, John Bulzacchelli, Woogeun Rhee, Alexander Rylyakov, Herschel Ainspan, Ben Parker, Michael Beakes, Aichin Chung, Troy Beukema, Petar Pepeljugoski, Lei Shan, Young Kwark, Sudhir Gowda and Dan Friedman

IBM T. J. Watson Research Center, Yorktown Heights, NY

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Transmission Channel Impairments

Eye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk

INPUT
Eye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk 500mV DATA = RAND Tx 600mVpd AGC Gain -6.02dB XTALK = NONE AGC 5.0GHz 0.00dB PKG=0/0 TERM = 5050/5050 IC = 3/3 400mV 300mV 200mV

Packaged SerDes Backplane trace Line card trace Edge connector

Signal Amplitude Vpd

500mV DATA = RAND Tx 600mVpd AGC Gain -5.48dB XTALK = NONE AGC 5.0GHz 0.00dB PKG=0/0 TERM = 5050/5050 IC = 3/3 400mV 300mV 200mV 100mV -0.0mV -100mV -200mV -300mV HSSCDR = 2.3.2-pre2 IBM Confidential Date = Sat 01/21/2006 12:00 PM PLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00us -400mV FFE = [1.000, 0.000] -500mV -100ps -50ps 0ps Time 50ps 100ps

Signal Amplitude Vpd

100mV -0.0mV -100mV -200mV -300mV HSSCDR = 2.3.2-pre2 IBM Confidential Date = Sat 01/21/2006 12:01 PM PLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00us -400mV FFE = [1.000, 0.000] -500mV -100ps -50ps 0ps Time 50ps 100ps

OUTPUT
Via stub
60 50 40 30 [OPEN,1e-8] Channel Response

10 0 -10 -20 -30

-40 -50 -60 -70 -80 -90 0Hz 2.0GHz 4.0GHz 6.0GHz Frequency 8.0GHz

10

-24.6dB @ 5GHz

0 -10 -20 -30 -40 10GHz

Pkg

Line card trace

Edge Backplane Edge connector 16 trace connector The Channel

|S11|,|S22|

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S21 |SDD21|

Line card trace

Pkg Rx IC

Tx IC [Meghelli (IBM) ISSCC 2006]

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10Gb/s SerDes Main Features

Tx with 1 baud-spaced 4-tap FFE Rx with 5-tap adaptive DFE and digital clock recovery LC-VCO based PLL for low noise clock generation 90nm CMOS technology

[Meghelli (IBM) ISSCC 2006]

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Transmitter Architecture
Key Features:
- Half-rate CML design - 4-tap FFE - Tap polarity control - ESD protection - 70mW (24mA main tap, no FFE)
VDD=1.0V IDACs & Bias Control 1/4 FFE Taps Pre-cursor Cursor 1st Post-cursor 2nd Post-cursor Full Scale 25% 100% 50% 25% DAC bits 4 6 5 4 ESD VDDA=1.2V 50 Out-P VDDA=1.2V 1 1/2 1/4 Out-N (10Gb/s)

1x VDDIO=1.0V D0 (2.5Gb/s) D1 D2 D3
1 1 1 1 2 2 2 2

4x

2x

1x

(5Gb/s) L 4:2 MUX L

sgn-1

sgn0 L

sgn1 L

sgn2 L

C2 (5GHz) From on-chip PLL

[Meghelli (IBM) ISSCC 2006]

A Low Power 10Gb/s Serial Link Transmitter in 90-nm CMOS A. Rylyakov et al., CSICS 2005

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Tx Output Eye Diagram @ 10Gb/s

ye F F E 1 1 0 .0 G b /s [O P E N ,1 e -8 ] N o X ta lk D 6 0 0 m V A d C G a in -6 .0 2 d B x pG NE A G C 5 .0 G H z 0 .0 0 d B R M = 5 0 5 0 /5 0 5 0 IC = 3 /0 %UI

No FFE, 24mA on main tap

Measured

2 .4 IB M C o n fid e n tia l R E Q O F S = 0 .0 0 p p m /0 .0 0 u s N 32 0 .0 0 0 ]

Simulated
50ps 100ps

50ps

0ps T im e

e F F E 4 1 0 . 0 G b / s [ O P E N , 1 e - 8 ] N o X t a lk 8 0 0 m VA G C G a in - 6 . 0 2 d B pd E A G C 5 .0 G H z 0 .0 0 d B R M = 5 0 5 0 /5 0 5 0 IC = 3 /0

FFE 4=[0, 85%, -15%, 0, 0]

2 . 4 I B M C o n f id e n t ia l E Q O F S = 0 . 0 0 p pD / E . 0 F u s 1 32 m /0 O 0 S T 0 .8 6 3 , -0 .1 3 7 , 0 .0 0 0 ]

0ps

0ps T im e

50ps

100ps

[Meghelli (IBM) ISSCC 2006]

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Receiver Architecture
From on-chip PLL (5GHz) C2-I Vcm 50 I C2-Q I-Clock control CDR logic Q-Clock control 8 VDDIO=1V
2 2 2 2 1 1 1 1

Phase rotator PI PI Q

D0 D1 D2 D3 (2.5Gb/s)

(10Gb/s)

In_P In_N T-Coil Compensation Network

Phase Edge 2:8 detector DMUX DFE Block

Data Amp

8:16 DMUX

VGA ESD VDDA=1.2V

Tap weights

DFE logic CML CMOS logic

Data Amp Edge Clock

VDD=1.0V

Key Features: - Half-rate design - 5-tap continuously adaptive DFE - Variable gain amplifier - Digital CDR - ESD protection (HBM & CDM) - 130mW (with DFE and CDR logic) 21

[Meghelli (IBM) ISSCC 2006]

DFE Approach
(+H1)

I L

I L

I L

(-H1)

Deven

Data

H1-5
(+H1)

Tap-feedback and weighting

Tap weights

(-H1)

I I I

Dodd L I L I L

On-chip DFE Logic

DFE Taps H1 H2 H3, H4, H5

Resolution 6 bits 5 bits 4 bits

I Offset Received eye

Amplitude

Key Features:
- Half-rate DFE with H1 speculation and dynamic H2-H5 feedback allows 2UI for settling - DFE algorithm maximizes vertical eye opening at the data slicing instant - Offset adjustment at all the slicer inputs

ISI

[Meghelli (IBM) ISSCC 2006]

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CDR Loop
Data Clock Z-1 Data Z-1 E D DMUX E D XORs Late Early From on-chip PLL I Rotator Control D/A Digital Q Rotator Filter Control D/A PI C2-I PI C2-Q Edge Clock
Receiver Jitter tolerance curve ( BER<1e-9)
1.4

Jitter Tolerance

Key Features:
- Fully digital loop - Can handle up to +/- 4000ppm frequency offset - Independent I,Q control
Sine Jitter (UI pp)

1.2 1 0.8 0.6 0.4 0.2 0

1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09

Tracking bandwidth ~9MHz

Modulation Frequency

[Meghelli (IBM) ISSCC 2006]

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Chip-to-Chip Link Experiments

SerDes1

Trace SerDes2
Trace Length 5GHz losses
(Tx module + board trace + Rx module)

Number of vias
3.8mm via stub / 1.8mm via stub / 1.8mm via through

10 (#1) 10 (#2) 15 20

12dB 10dB 25dB 15dB

2/0/0 0/2/0 4/2/0 0/0/2

SerDes1
Module

SerDes2
Module

Board Via stub Trace

[Meghelli (IBM) ISSCC 2006]

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Chip-to-Chip Measurement Results

Trace Length 5GHz losses (Tx module + board trace + Rx module) 12dB 10dB 25dB 15dB Number of vias 3.8mm via stub / 1.8mm via stub / 1.8mm via through 2/0/0 0/2/0 4/2/0 0/0/2

Horizontal Eye Opening (1e-9 BER)

Horizontal eye opening of the equalized 10 (#1) 10 (#2) eye at the receiver slicer input 60.00% 15
20

50.00%
DFE ONLY DFE ONLY

40.00% 30.00% 20.00%

DFE + FFE

DFE+FFE DFE FFE FFE ONLY

FFE ONLY

DFE + FFE

10.00% 0.00%

10" (#2) 15" [Meghelli (IBM) ISSCC 2006] Link

10" (#1)

DFE + FFE

DFE + FFE

20" 25

Preliminary Schedule

Dates may change with reasonable notice

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Next Time
Channels
Components
Chip packages, PCBs, Wires, Connectors

Modeling
Wires, Transmission Lines

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