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Block diagram
Complex mixer
(Re +
Spectrum
Real up mixer
Spectrum
Spectrum
Hardware implementation
FPGA state of the art
Multiplier are available in silicon structure (DSP blocks) Memory are available in silicon structures (true dual port memories)
s(t ) = sin (2 f c t )
Main blocks
Phase Accumulator Phase to Amplitude converter D/A converter Antialiasing filter
Phase Accumulator
Frequency Resolution
f clk M 2m f f c_res = clk 1 2m 200 MHz f c_res = 1 = 0,0466 HZ 232 High Frequency resolution requires high number of bits in the phase accumulator High number of bits in the phase accumulator requires a giant LUT Truncation is necessary Spurious fc =
Wolfgang Kogler Professor Horst Cerjak, 19.12.2005 Software Defined Radio Digital mixer and numerical oscillators
13
a) 2
0 2P
b)
2m
0 2P
DA converter
Tuning word M
f NCOmin =
f clock f clock = m ; N 2
f NCOout =
f clock f M = clock M N 2m
15
Q F4
Truncation error
F2 F1 I
F3
Phase error e bin (dec) 000 (0) 110 (6) 100 (4) 010 (2) 000 (0)
16
0000 (0) 0000 (0) 0001 (1) 0010 (2) 0011 (3)
Spur ratio
terror terror 2mP = M mod(2m P ) if M mod(2 m P ) 2m P 1
s(t ) = sin (2 f NCO t FP(t ) ) 2m P t FP(t ) = terror Carrier amplitude 2m 1 SPR = = m P 2 = 21+ P Spur amplitude 2
Wolfgang Kogler Professor Horst Cerjak, 19.12.2005 Software Defined Radio Digital mixer and numerical oscillators
17
Analog domain
DA converter errors:
Differential non linearity Integral non linearity Missing codes
Please note, that a frequency offset of the clock does not introduce spurious, but an corresponding frequency error!
Wolfgang Kogler Professor Horst Cerjak, 19.12.2005 Software Defined Radio Digital mixer and numerical oscillators
18