AUGUST 11, 2012

ADONIS S. SANTOS, ECE Instructor First Asia Institute of Technology and Humanities

Random Access Memories (RAMs) Dynamic RAMs

Basic DRAM Organization

Types of DRAMs FPM DRAMs EDO DRAMs BEDO DRAMs SDRAMs

Dynamic memory cells store a data bit in a small capacitor rather than in a latch.

A typical DRAM cell consists of a single MOS transistor (MOSFET) and a capacitor. The transistor acts as a switch and the capacitor stores the data bit.

A MOS DRAM cell

Advantage
the type of cell is very simple compare to SRAM cell allows very large memory arrays to be constructed on a

chip at a lower cost per bit

Disadvantage
Storage capacitor cannot hold its charge over an extended

period of time Additional memory circuitry and complicated the operation Much slower access time as compared to SRAM

The simplified DRAM circuit configuration.

R/W input determines the mode operation of the DRAM. A LOW in R/W line is a Write Mode and a HIGH is a Read Mode.
Refreshing capacitor charges is controlled through the REFRESH line.

A LOW in the row line disconnects the capacitor from the bit line thus trapping the charge (1 or 0) on the capacitor.

Writing a 1 into the DRAM memory cell

R/W is LOW DIN line must be

HIGH HIGH on the ROW line

The transistor acts as a closed switch connecting the capacitor to the bit line which allows the capacitor to charge to a positive voltage.

Writing a 0 into the DRAM memory cell

R/W is LOW DIN line must be LOW HIGH on the ROW

line

The transistor acts as a closed switch connecting the capacitor to the bit line. If the capacitor is storing a 0, it remains uncharged, or if it is storing a 1, it discharges.

Reading a 1 into the DRAM memory cell

R/W is HIGH HIGH on the ROW

line

The transistor acts as a closed switch connecting the capacitor to the bit line and thus to the output buffer (sense amplifier), so the data bit appears on the data output line (DOUT).

Refreshing a stored 1 in the DRAM memory cell

R/W is HIGH REFRESH line is

HIGH HIGH on the ROW line

A path from the charged capacitor to refresh buffer through the output buffer is created allowing the stored bit to be applied back to the capacitor thus replenishing the capacitor.

The major application of DRAMs is in the main memory of computers. Features common to most DRAMs (1M x 1 bit DRAM)
Address Multiplexing Read and Write Cycles Fast Page Mode Refresh Cycles

Simplified block diagram of a 1M x 1 DRAM

DRAMs use a technique called address multiplexing to reduce the number of address lines. The ten address lines are time multiplexed at the beginning of a memory cycle by the row address select (RAS) and the column address select ( CAS) into two separate 10-bit address fields.
Basic timing for address multiplexing

Row address is latched when RAS is LOW.

Column address is latched when CAS is LOW.

At the beginning of each read memory cycle, RAS and CAS go active (LOW) to multiplex the row and column addresses into the latches and decoders. For a read cycle, the R/W input is HIGH.

Read cycle timing

At the beginning of each write memory cycle, RAS and CAS go active (LOW) to multiplex the row and column addresses into the latches and decoders. For a write cycle, the R/W input is LOW.

Write cycle timing

A page is a section of memory available at a single row address and consists of all the columns in a row.
Fast page mode allows fast successive read or write operations at each column address in a selected row.

Fast page mode timing for a read operation

A row address is first loaded by RAS going LOW and remaining LOW while CAS is toggled between HIGH and LOW. A single row address is selected and remains selected while RAS is active. Each successive CAS selects another column in the selected row. After a fast page mode cycle, all of the addresses in the selected row have been read from or written into, depending on R/W. When CAS goes to its nonasserted state (HIGH), it disables the data outputs. Therefore, the transition of CAS to HIGH must occur only after valid data are latched by the external system.

Charge degrades (leaks off) with time and temperature. Typical refresh period of a DRAM is 8 ms to 16 ms Some devices have refresh period that can exceed 100 ms.
The two types of refresh operations: RAS-only refresh
consists of a RAS transition to the LOW (active) state, which latches the address of the row to be refreshed while CAS remains HIGH (inactive) throughout the cycle.

CAS before RAS refresh

initiated by CAS going LOW before RAS goes LOW. This sequence activates an internal refresh counter that generates the row address to be refreshed. This address is switched by the data selector into the row decoder.

Two basic refresh modes for refresh operation Burst refresh all rows in the memory array are refreshed consecutively each refresh period with normal read and write operations suspended. Distributed refresh
each row is refreshed at intervals interspersed between normal read or write cycles. Example: The memory in 1M x 1 DRAM has 1024 rows and an 8 ms refresh period. Find the refresh period of each row.
Each row must be refreshed every 8 ms/1024 = 7.8 us when

distributed refresh is used.

Major Types of DRAMS

Fast Page Mode (FPM) DRAM

Extended Data Output (EDO) DRAM

Burst Extended Data Output (BEDO) DRAM Synchronous (S) DRAM.

Fast Page Mode DRAM

most common has been the type used in computers until the

development of the EDO DRAM

Accessing memory addresses in the same row (on the same page) thus saves time over pure random accessing. CAS signal timing limits the rate at which the columns within a page can be addressed.

Extended Data Output DRAM

sometimes called hyper page mode DRAM

Similar to FPM DRAM except that CAS signal deassertion state does not affect valid data Current address is held until CAS is asserted again.

It speeds up the access time.

Burst Extended Data Output DRAM

an EDO DRAM with address burst capability

The concept is the same as with synchronous burst SRAM that the address burst feature allows up to four addresses to be internally generated from a single external address. It saves some access time.

Synchronous DRAM
operation is synchronized with the system clock which

also runs the microprocessor in a computer system.

The DRAM latches addresses, data, and control information from the processor under control of the system clock. This allows the processor to handle other tasks while the memory read or write operations are in progress.

References
Thomas L. Floyd, Digital Fundamentals, 9th Edition, Prentice Hall

M. Morris Mano, Michael D. Ciletti, Digital Design, 4th Edition,

Prentice Hall

Next Meeting
Lecture Topics Read-Only Memories (ROMs), Programmable ROMs