John G. Maneatis 1 , Jaeha Kim 1 , Iain McClatchie 1 , Jay Maxey 2 , Manjusha Shankaradas 2 True Circuits, Los Altos, CA 1 Texas Instruments, Dallas, TX 2 PDF file of JSSC paper linked at class web page. 2 Clock Generator PLLs for ASICs
Most ASICs PLLs for clock generation, but Use different frequencies and multiplication Graphics Processor Network Processor I/O Controller Your ASIC N F REF F OUT PLL 3 Optimal PLL Design For each F OUT and N, one must adjust loop parameters for both minimum jitter and stability
For clock generators (track input clocks) (e REF = 2tF OUT /N) Loop bandwidth : e N ~ e REF /20 Damping ratio : , ~ 1 Third-order pole : e C ~ e REF /2
Circuit parameters (e.g. I CH , R) must vary with F OUT and N!
4 Addressing Diverse Specifications Designing a different PLL for each ASIC Easier to meet the specification, but Verifying all designs is difficult and costly
Our Goal: One PLL design for all ASICs Only one design needs verification, but Loop parameters must adjust automatically to satisfy wide range of F OUT and N
5 Challenges Self-biased PLLs [Maneatis 96] adjust for F OUT
Achieve fixed e N /e REF and , indep. of PVT
But, Self-Biased PLLs do NOT adjust for N e N /e REF and , vary with N (want fixed) e C /e REF varies with N (want fixed)
This talk extends Self-Biased PLLs for wide ranges of N with a new loop filter network 6 Outline Introduction Review of Self-Biased PLLs Pattern Jitter Issues Loop Filter Architecture Implementation of Key Circuits Measured Results Conclusions 7 Second-Order PLLs
PFD CP I CH V CTL N CK OUT CK REF CK FB UP DN C 1 R VCO K V 2 N N N I O ) / s ( ) / s ( 2 1 ) / s ( 2 1 N ) s ( P ) s ( P e e , e , 1 C R 2 1 N = e , 1 V CH C 1 K I N 1 N e 8 Second-Order PLLs
PFD CP I CH V CTL N CK OUT CK REF CK FB UP DN C 1 R VCO K V ) 1 ( R CS I V CH CTL + = Oscillation frequency is supposed to be controlled by V CTL , that is by I CH /CS + I CH *R. In Ring Oscillators, frequency is more easily controlled by current, through tail biasing voltage. want tail current to have two components: ICH/CS + ICH*R. 9 Self-Biased PLLs PFD CP xI D CP xI D VCO K V =k/C B V CTL V BN N CK OUT CK REF CK FB UP DN V FF Replica-Feedback Biasing C 1 1/g m I D m g / 1 R = D CH I x I = B m VCO C g F = ) 1 ( R CS I CH + V BN biases the tail current in Ring Oscillator buffer stages. So want I D to have components: 10 Self-Biased PLLs PFD CP xI D CP xI D VCO K V =k/C B V CTL V BN N CK OUT CK REF CK FB UP DN V FF Replica-Feedback Biasing C 1 1/g m I D Op Amp adjust V BN so that NMOST ID matches currents in 1/gm and that from top charge pump. Notice: V CTL = V DD I CH / sC 1 d I D = (V DD V CTL )gm + I CH-ff = I CH (1/sC 1 + 1) Hence V BN will generate I-tail proportional to I CH (1/sC 1 + 1) 11 Maneatis self bias generator From 1996 Maneatis paper, which is very widely reference. PDF file linked at web page. 12 Self-Biased PLLs With Self-Biased PLLs
e N /e REF and , are constant with F OUT ,
BUT not with N
N x ~ C C N x 2 1 1 B REF N t e e N x ~ C C N x 4 1 B 1 , 13 Pattern Jitter / Spurious Noise Phase corrections every rising reference edge can cause disruptions to nearby output cycles Periodic noise pattern repeats every ref. cycle or N output cycles
Typical causes Charge pump imbalances or leakage Jitter in reference clock (aperiodic result) CK REF V CTL CK OUT SHORT 14 Shunt Capacitor Use third-order pole to extend disturbance with reduced amplitude over many output cycles
Problem with varying N using fixed capacitor Extended number of cycles NOT function of N Too few for large N Pattern jitter Too many for small N Instability FILTERED CK REF V CTL CK OUT 15 Proposed Loop Filter Use switched capacitor filter network to Output scaled amplitude error signal with N output cycle duration [Maxim 01]
Want a simple solution using this approach that is compatible with Self-Biased PLLs FILTERED CK REF V CTL CK OUT 16 Original Filter Network
Only need to filter feed-forward path V CTL V BN V FF Replica-Feedback Biasing C 1 CP CP UP DN 1/g m 17 Sampled Feed-Forward Network
Sample phase error and generate proportional current that is held constant for NT OUT
Sampled error is reset at end of ref. cycle Need V RST = V CTL as zero bias level
g m V CTL V BN V FF Replica-Feedback Biasing C 1 1/g m C 2 CP CP UP DN V RST 18 Complete Filter Network
Reset C 2 to V CTL directly Eliminates C 1 charge pump Equivalent feed-forward control gain Q O ~ N Q I
g m V CTL V BN V FF Replica-Feedback Biasing C 1 1/g m C 2 CP UP DN 19 Loop Dynamics With this new loop filter network we achieve
Need to keep e N /e REF and , constant with N Just scale charge pump current with 1/N (=x) More detailed analysis will show
Both are independent of F OUT , N, and PVT! N x ~ REF N e e N x ~ N x Q Q ~ I O , 1 B C C 2 1 REF N t e e 2 1 B C C C 4 1 = , 20 Complete Self-Biased CGPLL
PFD CP 1 CP 2 VCO Charge PumpBias Gen. (Prog. 1/NCurrent Mirror) V FS1 V FS2 V CTL V BN V BC V BC Clock Divider CK OUT CK REF CK FB Divide Ratio (N=1...4096) UP DN V BP g m (V FS1 +V FS2 ) V FF 1/g m LoopFilter Replica-Feedback VCOBias Gen. C 2 C 1 C 2 21 Self-Biased Filter Network
CP 1 CP 2 V FS1 V FS2 V FF V CTL C 2 C 1 C 2 S 1 S 2 Select Control UP DN en en V BN V BN 22 Filter Network Reset Switches
Can switch to V CTL independent of voltage level V BN V BR ~V CTL SEL_B SEL V CTL V FS V CTL V DD +V CTL sel_boosted 23 Filter Network Reset Switches When un-selected, sel = 0, sel_B = 1 (VDD). V_B = VDD, V_D = VDD + V_CTL, V_A = 0, V_C = V_BR = V_CTL. V_CA charged to V_CTL V BN V BR ~V CTL SEL_B SEL V CTL V FS V CTL V DD +V CTL sel_boosted A B C D 24 Filter Network Reset Switches When selected, sel_B = 0, sel = 1 (VDD). V_A = VDD, V_C = VDD + V_CTL, V_B = 0, V_D = V_BR. V_DB charged to V_BR or V_CTL V BN V BR ~V CTL SEL_B SEL V CTL V FS V CTL V DD +V CTL sel_boosted A B C D 25 Inverse-Linear Current Mirror Need to generate I CH = I D / N Use switches to adjust device size on input side For N=1~4096, need 12 binary weighted legs Need size range of 2048:1 Too much area! I OUT I IN V BD S 0 S 1 S 2 S 3 S 4 S 5 x2 x4 x1 x8 x16 x32 26 Multi-Stage Linear CM Solution to size problem with LINEAR control Use multiple device groups operating at different but ratioed current densities Can have large ranges using small devices
I OUT I IN V BD S 3 S 4 S 5 8:1 S 0 S 1 S 2 x2 x4 x1 x2 x4 x1 27 Multi-Stage Inverse-Linear CM Just diode connect multi-stage linear current source and use as input side of current mirror Can output gate bias of any device group Stable as long as gain blocks reduce currents I OUT V BD S 3 S 4 S 5 8:1 S 0 S 1 S 2 x2 x4 x1 x2 x4 x1 I IN 28 Complete Current Mirror
V BN I OUT V BC 8:1 8:1 8:1 S 9 S 10 S 11 S 6 S 7 S 8 S 3 S 4 S 5 I IN E 3 E 3 E 2 E 2 (N=14096) I OUT I IN
1 N S 0 S 1 S 2 x2 x4 x1 x1 V BD 29 Voltage-Controlled Oscillator
V FF V CTL V BN V BN V BP V BP V I - V I + V O + V O - V TAIL Buffer Stage VCOReplica-Feedback Bias Generator 11-Stage Ring Oscillator V BN V BP CK+ CK- CK+ CK- V REP 30 AV V DS Higher V DD AV AI L AI H I D AV V V TAIL V REP time Buffer Tail Node Matching
31 Modified VCO
V FF V CTL V BN V BN V BP V BP V I - V I + V O + V O - V TAIL (SHARED) Buffer Stage VCOReplica-Feedback Bias Generator 11-Stage Ring Oscillator V BN V BP V TAIL CK+ CK- CK+ CK- 32 Static Supply Sensitivity
32 33 PLL Implementation
Process Technology 0.13m N-well CMOS Nominal Supply Voltage 1.5V (designed for 1.2V) Total Occupied Area 0.38 x 0.48mm 2 VCO Frequency Range 30 ~ 650 MHz Multiplication Factor Range N = 1 ~ 4096 Power Dissipation 7mW @ 240 MHz, 1.5V 34 Measured Jitter vs N (240MHz)
35 PLL Jitter Measurement Summary 36 Conclusions Proposed PLL achieves wide N and F OUT range
PLL is self-biased with constant loop dynamics (e N /e REF , , ), independent of N, F OUT , and PVT
Sampled feed-forward network suppresses pattern jitter with effective e C that tracks e REF
Achieves relatively constant period jitter of less than 1.7% as N is scaled from 1 to 4096 37 References J. Maneatis et al., Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 424425.
J. Maneatis, Low-jitter process-independent DLL and PLL based on self-biased techniques, IEEE J. Solid-State Circuits, vol. 31, pp. 1723 1732, Nov. 1996.
A. Maxim et al., A low-jitter 1251250 MHz process-independent 0.18 m CMOS PLL based on a sample-reset loop filter, in IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 394395.
T. C. Lee and B. Razavi, A stabilization technique for phase-locked frequency synthesizers, in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 3942.
J. Maneatis and M. Horowitz, Precise delay generation using coupled oscillators, IEEE J. Solid-State Circuits, vol. 28, pp. 12731282, Dec. 1993.