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Programmable Logic

Design (PLD)
Programmable Logic Device
• An IC that contains large amount of
gates, flip flops and registers that are
interconnected on a chip

• Can be configured by the user to perform


a logic function

• Configured by programming of fuses


Problems of using standard ICs

• Require hundreds or thousands of ICs

• Require large board space

• Requires large amount of time and cost in


inserting, soldering and testing
Advantages of using PLD

• Less board space

• Faster in designing

• Higher reliability
Introduction

Input AND OR Output


Array Array
Classification of PLD
• Programmable Array Logic (PAL)
• Programmable Logic Array (PLA)
• Programmable Read Only Memory
(PROM)
• Complex Programmable Logic Device
(CPLD)
• Field Programmable Gate Array (FPGA)
Programmable Array Logic
(PAL)
Programmable Array Logic (PAL)

Input AND OR Output


Array Array

Programmable Fixed

The output comes back as an input

Programmable Fixed
4 input, 4 output, 3 AND-OR Structure
Example of a PAL Design
Example: Design a PAL

W(A,B,C,D) = ∑m(2,12,13)
X(A,B,C,D) = ∑m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) = ∑m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) = ∑m(1,2,8,12,13)
CD 00 01 11 10 CD 00 01 11 10
AB AB

00 00
1
01
01
1
11 11
1 1 1 1 1 1
10 10
1 1 1 1

CD 00 01 11 10 CD 00 01 11 10
AB AB

00 00
1 1 1 1 1
01 01
1 1 1 1
11
11
1 1 1
10
10
1 1 1 1
W = ABC’ + A’B’CD’
X = A + BCD
Y = A’B + CD + B’D’
Z = AC’D’ + A’B’C’D + ABC’ + A’B’CD’
= W + AC’D’ + A’B’C’D
Limitations
• Even if the terms are repetitive they cant
be reused as the AND outputs are fixed
therefore it is not possible to share the
AND outputs.
Programmable Logic Array
(PLA)
Programmable Logic Array (PLA)

Input AND OR Output


Array Array

Programmable Programmable

Implements SOP

Programmable Fixed
PLA
• The output and its compliment are available.

• Any SOP can be implemented

• But it should be seen to it that the terms are


shared to the maximum extent.

• Only limitations is the number of AND gates


available.
Example of PLA Design
Design a PLA circuit :

W(A,B,C,D) = ∑m(3,7,8,9,11,15)
X(A,B,C,D) = ∑m(3,4,5,7,10,14,15)
Y(A,B,C,D) = ∑m(1,5,7,11,15)
CD 00 01 11 10 CD 00 01 11 10
AB AB

00 00
1 1
01 01
1 1 1 1
11 11
1 1 1
10 10
1 1 1 1

CD 00 01 11 10
AB

00
1
01
1 1
11
1
10
1
W = A’CD + ACD + AB’C’
X = A’BC’ + A’CD + BCD + ACD’
Y = A’C’D + BCD + ACD
Exercise
Design the following using PAL and PLA

F1(A, B, C) = ∑m(3,5,6,7)
F2(A, B, C) = ∑m(0,2,4,7)
Programmable Read Only
Memory (PROM)
Programmable Read Only Memory (PROM)

Input AND OR Output


Array Array

Fixed (Decoder) Programmable

Implements Sum of Min-terms

Programmable Fixed
32 x 8 ROM
Design a circuit using ROM whcich accepts a 3 bit
binary no. and outputs the square of the number
B0 = A 0
B1 = 0
B2 = ∑m(2,6)
B3 = ∑m(3,5)
B4 = ∑m(4,5,7)
B5 = ∑m(6,7)

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