A Summary on A Network on Chip Architecture and Design Methodology

Network-on-Chip (NOC) : Architecture and the design methodology.

2-D mesh of switches and resources providing physical- architectural level design integration
Switch Resource2 Resource4
Resource3
Resource1
Processor
Core
Memory
FPGA
Customer
Hardware
block
Type of Resources
NOC on chip communication infrastructure OSI protocol stack
Physical
layer
Data
link
layer
Network
layer
Trans
port
layer
NOC design methodology
Phase1:Deriving Concrete architecture from NOC template defining
number of switches, shape of network, regions and resources
Phase2:Mapping application onto a concrete architecture to form a
concrete product
Basic module
Limitation of SOC and Algorithm on Chip

Time complexity
Mapping applications onto dedicated architectures is complex

Key issue : Tradeoff between generality and performance
Generality: Reusability of Hardware , Operating systems and development
practices
Performance : Delay, Cost, Power parameters are effective through
application specific structures
Efficient Way

Reuse
Components
Architectures
Applications and implementations
Heterogeneous implementation with different kind of resources for different tasks the most cost effective
solution.
Applications will be modeled as a large number of communicating tasks. The different tasks may have very
different characteristics
System platform
Software
Platform
Hardware
Platform
Key to reuse and integration of IP components is the communication from the physical to the system and
conceptual level
separate the specification of inter-task
communication from the
implementation of that communication;
separate the design, implementation
and verification of individual tasks from
the rest of the application
separate the development, optimization
and verification of the individual
resource from the network
infrastructure
NOC platform Techniques for High performance
Processing of multiple
ultra high data rate
streams and process in
real time
Multifunctional
Devices mix of
Entertainment,commu
nication,Remote
control
High Capacity wire
line, wireless
networks multiple
communication
protocols
simultaneously
Security and secrecy of
stored data
Advanced Devices Requisites
Challenges for Design

Verification
Testing
NOC platform effectively addresses these challenges by separating the computation resources from each other
and from the communication network
Trend to adapt layered approach of OSI reference model towards on Chip communication
optimization of memory sizes and data storage strategies for data intensive applications
System on a chip
Incorporating many different types of processing and memory elements, has to operate using Globally
Asynchronous Locally Synchronous (GALS) paradigm.
Avoids the problem of clock skew and leads to lower power consumption.
Routing in a two-dimensional mesh is
easy
Small switches
High capacity
Short clock cycle
Overall scalability
Network on Chip
Resource R
RNI(Resource Network
Interface)
Switch S Channel C
Chip-Level Integration of Communicating Heterogeneous Elements (CLICH)
For control handshaking and signaling bits will yield an effective data bus width of 256 bits
Connect NOCs and external modules
Data buffering
Packet reordering
Interface Modules
Backbone-platform-system design methodology (BPS).

Combination of design productivity
and system quality requirements
Metrics
Performance
Utilization
Capacity
Question and Answer

1)How does the Communication between the resources is implemented ?
A)Communication Between the resources is done by passing messages over the
mesh network through RNI(Resource Network Interface)

2)What is the role of wrappers
A) Regions are connected to the NOC by special communication arrangements
called wrappers W, which route packets so that regions are insulated from
external traffic

3)Is there a possibility to different communications in different modules of
network.
A)The concept of regions makes it possible to have different communication
mechanisms in different modules