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UNIT-8

FET AMPLIFIERS
By,
SHASHIDHAR M
Dept. of E & C
CIT, Gubbi

11/24/2014

Contents
1.

2.

Basics of JFET
FET Small signal analysis
A) JFET common source amplifier using fixed bias
B) Self-Bias JFET configuration
C) JFET common source amplifier using voltage divider configuration
D) JFET SOURCE-FOLLOWER (COMMON-DRAIN) CONFIGURATION
E) JFET COMMON-GATE CONFIGURATION

3.
4.

5.

Depletion Type MOSFET


Enhancement Type MOSFET
Designing of FET amplifiers

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1. Basics of JFET
Transistors
Bi-polar

(BJT)
NPN

Uni-polar

(FET)

PNP
n-channel p-channel
(JFET,MOSFET,MESFET..etc.)

The field-effect transistor (FET) is a three-terminal device used for a variety of


applications.
BJT transistor is a current-controlled device.
JFET transistor is a voltage-controlled device.
BJT transistor is a bipolar device.
FET is a unipolar device.

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1a. CONSTRUCTION AND CHARACTERISTICS OF JFET

n-type material forms the channel


between the embedded layers of ptype material.
Drain and source are connected to
the ends of then-type channel and
the gate to the two layers of p-type
material
JFET has two p-n junctions under
no-bias conditions

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1b. Working operation

When VGS =0 V, VDSSome


Positive Value:

gate and source terminal at


the same potential and a
depletion region in the low
end of each p-material
similar to the distribution of
the no-bias conditions.
The instant the voltage VDD
(VDS)
establishes
the
conventional current ID
With VGS=0V, ID=IS.

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Contd..

For smaller value of VDS, ID increases linearly.

As VDS increases, width of the channel gets reduces and hence


resistance of the channel increases.

If VDS is increased to a level where it appears that the two


depletion regions would touch a condition referred to as pinchoff will result.

The level of VDS that establishes this condition is referred to as


the pinch-off voltage and is denoted by VP.

ID maintains a saturation level defined as IDSS


because of small channel with high current density

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Contd..

IDSS is the maximum drain current for a JFET and is defined by


the conditions
VGS = 0 V and VDS >|VP|
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when VGS < 0V


VGS is the controlling voltage of the
JFET
the result of applying a negative
bias to the gate is to reach the
saturation level at a lower level
of VDS
when VGS= VP will be sufficiently
negative
to
establish
a
saturation
level
that
is
essentially 0 mA, and for all
practical purposes the device
has been turned off.

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The level of VGS that results in ID 0 mA is defined by VGS = VP,


with VP being a negative voltage for n-channel devices and a
positive voltage for p-channel JFETs
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JFET as Voltage-Controlled Resistor


The region to the left of the pinch-off locus is referred to
as the ohmic or voltage-controlled resistance region.

JFET can actually be employed as a variable resistor


whose resistance is controlled by the applied gate-tosource voltage.

where ro is the resistance with VGS =0 V and rd the


resistance at a particular level of VGS

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1c.Transfer characteristics

Plot between input voltage and output current(VGS v/s ID)


The relationship between ID and VGS is defined by Shockleys equation

Substituting VGS = 0V

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when VGS = Vp

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2. FET Small signal analysis

Features of FET amplifiers


excellent voltage gain
high input impedance
low-power consumption
good frequency range
minimal size and weight
BJT had an amplification factor (beta), the FET has a
transconductance factor, gm.
Applications:
FET can be used as a linear amplifier.
FET devices are also widely used in high-frequency applications
and in buffering (interfacing) applications.

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2a.Configurations of FET amplifier

Common
source

inverted,
amplified signal

Common Drain unity gain with no inversion


Common gate

gain with no inversion

Important circuit features


voltage gain(Av)
input impedance(Zi), and
output impedance(Zo)
Current gain is an undefined quantity

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2b.FET SMALL-SIGNAL MODEL

Small signal model is required in the ac analysis of FET


amplifiers.
The gate-to-source voltage controls the drain-to-source
(channel) current of an FET.
i.e. ID VGS
ID VGS
ID = gm VGS
where gm is called as trans-conductance of FET

gm is also represented by yfs,and it stands for forward


transfer admittance
On specification sheets, gm is provided as yfs

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Graphical determination of gm

gm increase as we progress from VP to IDSS. Or, in other


words, as VGS approaches 0 V, the magnitude of gm increases.

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Calculating gm at various bias points.

Slope of the characteristic at the


point of operation

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Mathematical Definition of gm

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VGS = 0v slope of transfer characteristics is maximum or is gm


maximum

Eqn of gm becomes

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Exercise on gm
For a JFET with IDSS = 8 mA and VP = - 4V, determine
(a) Maximum gm
(b) Value of gm when VGS = -1.5V
Solutions

(a)

Maximum gm when VGS = 0V

(b)

When VGS = -1.5V

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Plotting gm versus VGS

When VGS = VP,


gm is zero

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When VGS = 0V,


gm is maximum

Example
Plot gm versus ID with IDSS = 8mA and VP = -4V

gm

2 I DSS

| VP |

g m0

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VGS
1

V
P

2 I DSS

| VP |

Effects of ID on gm

Relationship between ID dan gm can be obtained


from Shockley Equation:
VGS
1

VP

ID
I DSS

gm can also be written as


VGS
g m g m0 1

P
g m g m0

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ID
I DSS

Plotting gm versus ID

g m g m0

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ID
IDSS

g m0
where

2 I DSS

| VP |

ID

gm

IDSS

gm0

IDSS/2

0.707 gm0

IDSS/4

0.5 gm0

0 mA

Example
Plot gm versus ID with
IDSS = 8mA and VGS = -4V

gm

ID

gm0

IDSS

0.707 gm0

IDSS/2

0.5 gm0

IDSS/4

0 mA

g m g m0

g m0

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ID
IDSS

2 I DSS

| VP |

FET Impedance

FET input impedance, Zi is sufficiently large.


Usually in the range of 109 (1000M)

FET output impedance, Zo On FET specification


sheets, the output impedance will typically appear as
yos with the units of S

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Definition of rd using FET drain characteristics.

The more horizontal the curve, the greater the output


impedance.
VGS remain constant when rd is determined

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FET AC equivalent circuit.

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Example

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A.JFET common source amplifier using


fixed bias

Zi FET R G
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Determining Zo.

Set Vi 0

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Determining Av

Vo = -g m Vgs rd || R D
Vgs = Vi
Vo = -g m Vi rd || R D
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A v = Vo Vi = -g m rd || R D
A v = Vo Vi = -g m R D when rd 10R D

Example
IDSS=10mA
VP=-8V

Determine the
following for the network
1. g m and rd
2. Z i
3. Zo
4. A V
5. A V ignoring effect of rd

yOS=40S
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IDQ=5.625mA
VGSQ=-2V

Solutions
IDQ=5.625mA
VGSQ=-2V
IDSS=10mA
VP=-8V

gm0

2I DSS 2 10mA
=
=
= 2.5mS
VP
8V

rd =

1
1
=
= 25 k
y os 40S

Z i = R G = 1M

yOS=40S
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Zo = rd || R D = 2k || 25k = 1.85k

Solutions..
Zo = rd || R D = 2k || 25k = 1.85k

AV =

Vo
= -g m R D || rd
Vi

With rd , A v = -3.48

AV =

Vo
= -g m R D
Vi

Without rd , A v = -3.76

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B. Self-Bias JFET configuration.

JFET AC equivalent circuit.

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Redrawn Network

Zi = ?
Zo = ?
AV = ?
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C. Unbypassed RS
Initially the resistance rd will be left out

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Zo: To find Zo, set Vi= 0V

Vi= 0V

Vi= 0V

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wkt

Applying KCL

but
hence

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If rd is included..

Vi=0v

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Voltage gain(Av):-

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D. JFET common source amplifier using voltage divider configuration

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E. JFET SOURCE-FOLLOWER
(COMMON-DRAIN) CONFIGURATION

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Zo:
To find Zo set Vi = 0V

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Av:

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F. JFET COMMON-GATE CONFIGURATION

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Zi: Zi = Rs || Zi
To find Zi :Let

Apply KCL to node a

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Zo:

Av:

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MOSFET amplifiers
MOSFET

Enhancement type

N-channel

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P-channel

Depletion type

N-channel

P-channel

3. Depletion type MOSFET


Circuit symbol

Structure

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Basic Operation and Characteristics


VGS = 0V and VDS a positive voltage:
Electrons are
attracted by a
positive potential

ID = IDSS when VGS = 0V

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Contd.
VGS is negative and VDS a positive voltage:

Electrons are repelled


by negative potential at
gate

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Characteristics of D-MOSFET
Positive VGS attracts electrons

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Ac equivalent of D-MOSFET
Equations of ID and VGS remains same as in
JFET

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Exercise
For the following network determine the following if VGSQ = 0.35, IDQ = 7.6mA
A) Determine gm and compare with gm0
B) Find rd
C) Sketch the ac equivalent network

D) Find Zi, ZO and AV

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4. Enhancement type MOSFET


Symbol

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Structure

Working operation
When VGS = 0V and VDS is positive ID = 0mA.

When VGS and


VDS are positive

The level of VGS that


results in the significant
increase in drain current is
called
the
threshold
voltage (VT or VGS(Th))
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AC equivalent of E-MOSFET

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Mathematical representation of gm in EMOSFET

In E-MOSFET relationship between output


current and controlling voltage is defined by

where

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Contd..

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1)E-MOSFET DRAIN-FEEDBACK
CONFIGURATION

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Input Impedence(Zi):

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Output Impedence(Zo):-

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Voltage Gain (AV):-

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Contd..

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Exercise
(a) Determine gm.

(b) Find rd.


(c) Calculate Zi with and
without rd. Compare results.
(d) Find Zo with and without
rd. Compare results.
(e) Find Av with and without
rd. Compare results.

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E-MOSFET VOLTAGE-DIVIDER CONFIGURATION

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5. DESIGNING FET AMPLIFIER NETWORKS


Example1
Design the fixed-bias network to have an ac gain of
10.

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Example 2:
Choose the values of RD and RS for the network that
will result in a gain of 8 using a relatively high level
of gm for this device defined at VGSQ = 1/4VP.

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THANK YOU

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