Fundamentals of Processor

Design
Using figures from
Rapid Prototyping of Digital Systems
by Hamblen and Furman

Spring 2014

EE 310 Course Topics

Digital
Hardware Design

Rapid Prototyping
with FPGAs

VHDL

Computer
Organization

Overview
Behavioral model is provided in Hamblen
You will design a structural model over the
course of the semester

ALU
Registers
Controller
P3

The Framework
Computer organization; the role of the
processor
Processor architecture vs. organization
Processor organization in detail
Processor performance
Will learn about processor design and
organization in general

one specific example

Building Blocks of a Computing System

Processor

Datapath
Registers (register file)
ALU
Interconnection
structure
Interface with memory

Instruction path
Registers
Interface with memory

Control Unit

Memory
I/O

A softwareprogrammable computing
system also needs
Compiler
Operating System
Middleware

Structural vs. dynamic

description of a processor
Pure hardware vs.
software-programmable
system---and hybrids

Embedded vs. Desktop Processors

Embedded
Priority is predictable
behavior
Oriented toward
interaction with the
physical world

Desktop
Priority is
computational speed
Buffered interfaces to
the external
environment

Different types of computing systems

Transformational no time concept
Interactive its own speed
Reactive speed of environment

Computer Hardware Organization

Processor

Memory

Interconnection
Structure

I/O

The interconnection structure is normally one or more busses

Bus = multiple signals, going to the same places
Bus can have multiple drivers, need to worry about control

Architecture

Organization

The programmers view of the

The machinery or structure
computer (usually the
that underlies the
assembly language
architecture---the
programmers view)

What it does

Analogy: The architect decides

how the building will look

The ISA (Instruction Set

Architecture) - defines the
meaning of the binary numbers
that tell the processor what to
do, and with what
Defines the
hardware/software interface
Defines the dynamic/static
interface between the
hardware and the compiler

microarchitecture

How it does it
Analogy: The structural
engineer defines the
materials and the loadbearing frame structure--how the building is put
together
Precisely, the collection of
functional units (registers,
ALU, and control unit) and
how they are
interconnected

Instruction Set Architecture (ISA):

Dynamic/Static Interface
Program

Static

Architecture
Machine

D/SI
Dynamic

The ISA defines the (dynamic/static) interface

between the program (HLL) and the machine

Components of the ISA

Opcodes

Defines what is to be done to the operands

specified by the address field

Addressing modes

There are multiple ways to specify the data to

use: either explicitly in the instruction
(immediate), or by specifying its location (in
various ways)

Data types

Defines how a number is represented and the

number of bits for that representation

Multiple Descriptions of a Processors

Organization
Structure

Dynamics temporal
behavior

All the functional

units and how they
are interconnected

Block diagram

Instruction cycle and

clocking methodology
State and flow
diagrams

Basic Datapath
From
Data Bus

Control Unit selects

Registers and ALU function

Register
File

To
Address Bus

To
Data Bus
ALU

Status to
Control Unit

Structure of a Processor
Control Unit
Program
Counter

Address
Generation
Logic

Stack
Pointer

Bus

Address
Register
Control
Circuitry Control

Data Processing Unit

Status
Register

ALU

Signals

Instruction
Register

Data
Register

Register
File

Basic Processor Design Steps

1. Establish datapath requirements from instruction set
each instruction is implemented by register transfers
datapath must include registers for ISA and
control/status registers
datapath must support each register transfer via the
interconnection structure
2. Select datapath components and establish clocking
methodology
3. Design datapath meeting the requirements
4. Determine setting of control points that effects the
register transfer
5. Design the control logic

Organization of a Simple Processor

Processor
Memory
PC

Input/Ouput

IR

AC

MAR

ALU
Control
Unit

MDR

Address Bus
Data Bus

Need to define control and

status lines for memory & I/O

Need to define
interconnection structure

IR

00 00

ALU

register_AC

16

+1

00 00

PC

00
8

MAR
Memory
00: 02 11
01: 00 12
02: 01 10
03: 03 03
MDR

16

00

10: 00 00
11: 00 04
12: 00 03

MW = 0

02 11

Figure 8.7 Datapath. Values shown after applying reset.

MW is
Memory Write
control line

Register Definitions
Instruction-oriented
registers

PC (Program Counter)
points to the address
of the (current/next)
instruction
IR (Instruction
Register) holds the
current instruction

Data-oriented registers

AC (accumulator) holds
one operand for ALU;
receives result from ALU
MAR (Memory Address
Register) holds location
of information to be
loaded from memory
MDR (Memory Data
Register) holds data
coming from/going to
memory; other operand
for ALU

Instruction Format

Opcode
15

Address
8 7

1. The width of the opcode is determined (in part)

by the number of instructions in the ISA.
2. In general, the number of operands will vary,
depending on the instruction

Instruction Set

ADDI - add immediate, signed, sign extend address to 16 bits

SHL - use lower 4 bits of address field, unsigned. Other 4 bits are
"0000".

Processor Instruction Cycle

Fetch Next
Instruction

Decode
Instruction

Execute
Instruction

Details of Instruction Cycle

FETCH

DECODE

MAR = PC*
IR = MDR
PC = PC + 1
Read Memory

MAR = IR
Read
Memory

Opcode=STORE
Opcode=ADD

EXECUTE

AC = AC + MDR

MAR set in
EXECUTE step

Opcode=LOAD
AC = MDR

MDR = AC
Write Memory

IR

00 00

ALU

register_AC

16

+1

00 00

PC

00
8

MAR
Memory
00: 02 11
01: 00 12
02: 01 10
03: 03 03
MDR

16

00

10: 00 00
11: 00 04
12: 00 03

MW = 0

02 11

Figure 8.7 Datapath. Values shown after applying reset.

MW is
Memory Write
control line

IR

02 11

ALU

register_AC

16

+1

Memory
00: 02 11
01: 00 12
02: 01 10
03: 03 03
MDR

Note: MAR=PC
is moved to
Execute state
to save a clock
cycle!

00 04

PC

01

MAR

01

1. Read memory
2. IR = MDR
3. PC = PC + 1

10: 00 00
11: 00 04
12: 00 03
00 12

Figure 8.8 Register transfers in the ADD instructions Fetch State.

IR

1. Decode opcode
2. MAR = IR
3. Start memory
read

00 12

12

ALU

register_AC

00 04

PC
MAR
Memory
00: 02 11
01: 00 12
02: 01 10
03: 03 03
MDR

02
01

12

10: 00 00
11: 00 04
12: 00 03
00 12

Figure 8.9 Register transfers in the ADD instructions Decode State.

IR

00 12
00 04

00 03
ALU
00 07
register_AC

1. AC = AC + MDR
2. MAR = PC
3. Go to FETCH

00 04

PC

02

16
MAR
Memory
00: 02 11
01: 00 12
02: 01 10
03: 03 03
MDR

12

02

16

10: 00 00
11: 00 04
12: 00 03
00 03

Figure 8.10 Register transfers in the ADD instructions Execute State.

Figure 8.13 Simulation of the simple computer program.

-- Simple Computer Model scomp.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
ENTITY SCOMP IS
PORT( clock, reset
: IN STD_LOGIC;
program_counter_out
: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
register_AC_out
: OUT STD_LOGIC_VECTOR(15 DOWNTO 0 );
memory_data_register_out
: OUT STD_LOGIC_VECTOR(15 DOWNTO 0 ));
memory_address_register_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0 );
memory_write_out
: OUT STD_LOGIC);
END SCOMP;
ARCHITECTURE a OF scomp IS
TYPE STATE_TYPE IS ( reset_pc, fetch, decode, execute_add, execute_load, execute_store,
execute_store2, execute_jump );
SIGNAL state: STATE_TYPE;
SIGNAL instruction_register, memory_data_register : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL register_AC
: STD_LOGIC_VECTOR(15 DOWNTO 0 );
SIGNAL program_counter
: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL memory_address_register
: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL memory_write
: STD_LOGIC;
BEGIN

-- Use Altsyncram function for computer's memory (256 16-bit words)

memory: altsyncram
GENERIC MAP (
operation_mode => "SINGLE_PORT",
width_a => 16,
widthad_a => 8,
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
-- Reads in mif file for initial program and data values
init_file => "program.mif",
intended_device_family => "Cyclone")
PORT MAP (wren_a => memory_write, clock0 => clock,
address_a =>memory_address_register, data_a => Register_AC,
q_a => memory_data_register );
-- Output major signals for simulation
program_counter_out <= program_counter;
register_AC_out
<= register_AC;
memory_data_register_out <= memory_data_register;
memory_address_register_out <= memory_address_register;

PROCESS ( CLOCK, RESET )

BEGIN
IF reset = '1' THEN
state <= reset_pc;
ELSIF clock'EVENT AND clock = '1' THEN
CASE state IS
-- reset the computer, need to clear some registers
WHEN reset_pc =>
program_counter
<= (others => '0');
register_AC
<= (others => '0');
state
<= fetch;
-- Fetch instruction from memory and add 1 to PC
WHEN fetch =>
instruction_register <= memory_data_register;
program_counter
<= program_counter + 1;
state
<= decode;
-- Decode instruction and send out address of any data operands
WHEN decode =>
CASE instruction_register( 15 DOWNTO 8 ) IS
WHEN "00000000" =>
state <= execute_add;
WHEN "00000001" =>
state <= execute_store;
WHEN "00000010" =>
state <= execute_load;
WHEN "00000011" =>
state <= execute_jump;
WHEN OTHERS =>
state <= fetch;
END CASE;

-- Execute the ADD instruction

WHEN execute_add =>
register_ac
<= register_ac + memory_data_register;
state
<= fetch;
-- Execute the STORE instruction
-- (needs two clock cycles for memory write and fetch mem setup)
WHEN execute_store =>
-- write register_A to memory, enable memory write
-- load memory address and data registers for memory write
state
<= execute_store2;
--finish memory write operation and load memory registers
--for next fetch memory read operation
WHEN execute_store2 =>
state
<= fetch;
-- Execute the LOAD instruction
WHEN execute_load =>
register_ac
<= memory_data_register;
state
<= fetch;
-- Execute the JUMP instruction
WHEN execute_jump =>
program_counter <= instruction_register( 7 DOWNTO 0 );
state
<= fetch;
WHEN OTHERS =>
state <= fetch;
END CASE;
END IF;
END PROCESS;

-- Execute the ADD instruction

WHEN execute_add =>
register_ac
<= register_ac + memory_data_register;
state
<= fetch;
-- Execute the STORE instruction
-- (needs two clock cycles for memory write and fetch mem setup)
WHEN execute_store =>
-- write register_A to memory, enable memory write
-- load memory address and data registers for memory write
state
<= execute_store2;
--finish memory write operation and load memory registers
--for next fetch memory read operation
WHEN execute_store2 =>
state
<= fetch;
-- Execute the LOAD instruction
WHEN execute_load =>
register_ac
<= memory_data_register;
state
<= fetch;
-- Execute the JUMP instruction
WHEN execute_jump =>
program_counter <= instruction_register( 7 DOWNTO 0 );
state
<= fetch;
WHEN OTHERS =>
state <= fetch;
END CASE;
END IF;
END PROCESS;

-- memory address register is already inside synchronous memory unit

-- need to load its value based on current state
-- (no second register is used - not inside a process here)
WITH state SELECT
memory_address_register <= "00000000"
WHEN reset_pc,
program_counter
WHEN fetch,
instruction_register(7 DOWNTO 0) WHEN decode,
program_counter
WHEN execute_add,
instruction_register(7 DOWNTO 0) WHEN execute_store,
program_counter
WHEN execute_store2,
program_counter
WHEN execute_load,
instruction_register(7 DOWNTO 0) WHEN execute_jump;
WITH state SELECT
memory_write <=
'1'
WHEN execute_store,
'0'
WHEN Others;
END a;

Performance
Performance of a processor is determined by:

Instruction count (why?)

Clock cycle time
Clock cycles per instruction

Processor design (datapath and control) will

determine:

Clock cycle time

Clock cycles per instruction

There is more

Design of the control unit

Memory technology and organization
Design of the I/O interfaces
Design of the ALU

Computer arithmetic and hardware

implementations

Design of the languages

Communication and networking

References
Computer Architecture and Organization, John
P. Hayes, Third ed., 2002
MCU datasheets
Hamblen, Hall and Furman, Rapid Prototyping
of Digital Systems, SOPC Ed.