Digital Electronics

Combinational Circuits
Part 1

Israt Ferdous

Objectives
Arithmetic Circuits
Adder
Subtractor
Carry Look Ahead Adder

BCD Adder
Multiplier

Combinational Circuit Design

Procedure
Given a problem statement:

Determine the number of inputs and outputs

Derive the truth table
Simplify the Boolean expression for each output
Produce the required circuit

Designing Combinational Logic

Circuit
Design a logic circuit that has three inputs, A,B and C, and whose
output will be HIGH only when a majority of the inputs are HIGH.
Step1. Set up the truth table

ABC

ABC

ABC

ABC

Step2. Write the AND term for each case where the output is 1

Step 3. Write the SOP expression for the output

Step 4. Simplify the output expression

Step 5: Implement the circuit

Adder
Design an Adder for 1-bit numbers?

Adder
Design an Adder for 1-bit numbers?
1. Specification:
2 inputs (X,Y)
2 outputs (C,S)

Adder
Design an Adder for 1-bit numbers?
1. Specification:
2 inputs (X,Y)
2 outputs (C,S)

2. Formulation:
X

Adder
Design an Adder for 1-bit numbers?
1. Specification:

3. Optimization/Circuit

2 inputs (X,Y)
2 outputs (C,S)

2. XFormulation:
Y
C

Half Adder
This adder is called a Half Adder
Q: Why?

Full Adder
A combinational circuit that adds 3 input bits to
generate a Sum bit and a Carry bit

Full Adder
A combinational circuit that adds 3 input bits to
generate a Sum bit and a Carry bit
X

Full Adder
A combinational circuit that adds 3 input bits to
generate a Sum bit and a Carry bit
Sum

YZ

00
0

00
0

Carry
X

YZ

01
1

11
0

10
S = XYZ + XYZ
1
+ XYZ +XYZ
0
=XYZ

01
0

11
1

10
0

1
C = XY + YZ + XZ

Binary Adder(Normal Design)

Full Adder

S = xy'z'+x'yz'+x'y'z+xyz = x y z
C = xy + xz + yz

x
S
y

y
z
C

Full Adder = 2 Half Adders

Manipulating the Equations:
S= XY Z
C = XY + XZ + YZ

Full Adder = 2 Half Adders

Manipulating the Equations:
S=(XY)Z
C = XY + XZ + YZ
= XY + XYZ + XYZ + XYZ + XYZ
= XY( 1 + Z) + Z(XY + XY)
= XY + Z(X Y )

Full Adder = 2 Half Adders

Manipulating the Equations:
S=(XY)Z
C = XY + XZ + YZ = XY + Z(X Y )

Think of
Z as a
carry in

Src: Manos Book

Bigger Adders
How to build an adder for n-bit numbers?
Example: 4-Bit Adder

Inputs ?
Outputs ?
What is the size of the truth table?
How many functions to optimize?

Bigger Adders
How to build an adder for n-bit numbers?
Example: 4-Bit Adder

Inputs ? 9 inputs
Outputs ? 5 outputs
What is the size of the truth table? 512 rows!
How many functions to optimize? 5 functions

Binary Parallel Adder

To add n-bit numbers:
Use n Full-Adders in parallel
The carries propagates as in addition by hand
Use Z in the circuit as a Cin
1 0 0 0

0101
0110
1011

Binary Parallel Adder

To add n-bit numbers:
Use n Full-Adders in parallel
The carries propagates as in addition by hand

Src: Manos Book

This adder is called ripple carry adder

Ripple Adder Delay

Assume gate delay = T

8 T to compute the last

carry

Total delay = 8 + 1 = 9T

1 delay form first half

adder
Delay = (2n+1)T

Src: Course CD

Subtraction (2s Complement)

How to build a subtractor using 2s
complement?

Subtraction (2s Complement)

How to build a subtractor using 2s
complement?

Src: Manos Book

S = A + ( -B)

Adder/Subtractor
How to build a circuit that performs both
addition and subtraction?

Adder/Subtractor
0 : Add
1: subtract

Src: Manos Book

Using full adders and XOR we can build an Adder/Subtractor!

Binary Parallel Adder (Again)

To add n-bit numbers:
Use n Full-Adders in parallel
The carries propagates as in addition by hand

Src: Manos Book

This adder is called ripple carry adder

Ripple Adder Delay

Assume gate delay = T

8 T to compute the last

carry

Total delay = 8 + 1 = 9T

1 delay form first half

adder
Delay = (2n+1)T

How to improve?
Src: Course CD

BCD Adder
BCD digits are valid for decimal numbers 0-9
Addition of two BCD numbers will generate an output,
that may be greater than 1001 (9).
In such cases, the BCD number 0110 is added to the
result as a correction step
When adding two BCD numbers, the maximum result
that can be obtained is:
9 + 9 = 18
If we include a carry in bit, then the maximum result that can
be obtained is: 19 (10011)
Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6
needs to be added to bring them to correct BCD format.

Adding two BCD numbers

Truth Table
The truth table defines the
outputs when two BCD
numbers are added
The function F is 1 for all invalid
BCD digits, and therefore acts
as a BCD verifier
To minimize the expression, a 5
variable can be used, or:
-A 4 variable k map can be
used to minimize the function F,
and
-The result is ORed with CO,
since the function is always 1
whenever CO is 1
* From course CD

Adding two BCD numbers

Minimization
F

Z1Z0
Z3Z2
00
00
0

01
0

11
0

10
0

01

11

10

F = Z3Z2 + Z3Z1 + CO

Adding two BCD numbers

Circuit

B3 B2B1B0

A3A2A1A0

4-bit Binary
Adder

Cout

Z3 Z2 Z1 Z0

0
Correction
Step

4-bit Binary
Adder
S3 S2 S1 S0

Carry In

Adding two BCD numbers Steps

The two 4-bit BCD inputs are added by the 4-bit binary
adder to produce the sum Z3Z2Z1Z0 and a Carry Out
(Cout)
When Cout =0, the correction step executes by adding 0000
to Z3Z2Z1Z0, and the output remains the same
When Cout =1, the correction step adds 0110 to Z3Z2Z1Z0
to generate the corrected output
The output carry is the same as Cout
If additional decimal digits need to be added, the BCD adder
can be cascaded, with the output carry of one phase
connected to the input of the other

Parallel Adders
Reduce the carry propagation delay
Employ faster gates
Look-ahead carry (more complex mechanism, yet faster)
Carry propagate: Pi = AiBi
Carry generate: Gi = AiBi
Sum: Si = PiCi
Carry: Ci+1 = Gi+PiCi
C0 = Input carry
C1 = G0+P0C0
C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

Carry Look-ahead Adder (1/2)

Logic diagram

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

Carry Look-ahead Adder (2/2)

4-bit carry-look
ahead adder
Propagation delay
of C3, C2 and C1
are equal.

Fig. 4.12 4-Bit Adder with Carry Look-ahead

Exercise

From the fig, an analog-to-digital converter is monitoring the dc

voltage of a 12V storage battery on an orbiting spaceship. The
converters output is a four-bit binary number, ABCD,
corresponding to the battery voltage in steps of 1V, with A as
the MSB. The converters binary outputs are fed to a logic
circuit that is to produce a HIGH output as long as the binary
value is greater than (0110)2=(6)10; that is the battery voltage is
greater than 6V. Design the logic circuit.

Exercise