Introduction to SOP Technologies

ECE/ME/MSE 6776A
Introduction to SOP which includes

SOC, MCMs, SIP, 2.5D, 3D ICs,
3D Systems
Prof. Rao R. Tummala
nD
2
Joseph M. PettitClass
Endowed Chair
Professor in ECE & MSE
by System
Scaling
Director,SOP
3D Systems
Packaging Research
Center
Todays Class
What is SOP?
What are SOP Technologies?
Industry Collaborations in SOP at GT
GT PRC model for R&D
Educational Programs in SOP at GT
Slide 2 | 08-20-2015
ECE/ME/MSE 6776 SOP by System Scaling
GT APPROACH TO SYSTEM
SCALING
Research
Industry Collaboration
Education
Slide 3 | 08-18-2015
SOP BY SYSTEM SCALING
Slide 4 | 08-20-2015
An Example of System Scaling vs.

Transistor Scaling
1,000
10
00
X
System Scaling (I/O Pitch)
5X
1,000
100
100
Gap
Transistor Scaling (Node)
0
1960
10
1970
1980
1990
Year
2000
Courtesy: S.S. Iyer, IBM

Slide 5 | 08-18-2015
2010
2020
bump pitch(um)
Node dimension (nm)
10,000
Packaging to date: Single or Multiple ICs

Plastic
Packaging
Leaded Packaging
Ceramic MCM
Packaging
MCM
Organic
Packaging
3D Packaging
BGA Packaging
3D ICs with TSV

Memory
Memory
Memory
Memory
Logic
Build Up
Organic
GTs 3D Interposer
SIPs
Memory
40 Memory
um
Memory
Memory
Glass Package
CPU
GPU
PWB
3D Photonics
Logic
Photo-detector array
3 1
Logic
Laser array (VCSEL)
2
5
Fiber
Slide 6 | 08-18-2015
Sources: Infineon, Georgia Tech, Stats, ST Ericsson
What is SOP?
SOP is like SOC; instead of being on an IC, it is on a

package but with all heterogeneous system functions
SOC: Miniaturization at IC Level
SIP: Miniaturization at Module level
SOP: Miniaturization at System Level
Slide 7 | 08-20-2015
SOP Concept @ GT
Total System Miniaturization

Optimized System Components: CMOS and Non-CMOS
Miniaturize System in Two Ways:
1. Shrink System bulkiness & hierarchy to 2: devices and system
2. All components are miniaturized & embedded at micro & nano
scale
Optimize for cost and performance between device &

system
Slide 8 | 08-20-2015
PRC Vision of Digital Convergence by 1000X
Digital + Analog + RF +
Optical + Sensors
Slide 9 | 08-20-2015
Computing/Internet
Digital Audio
Digital Imaging/Video
Cellular/Wireless
GPS/Satellite
Sensors
And, of course, timekeeping!
SOP @ PRC
Package is the System
System: Convergent Computing,

Communication, Consumer & Biomedical
SOP
Slide 10 | 08-20-2015
What is Packaging in the new Era?
Old Era: The SOC or Microelectronics Era (1965---)

Interconnecting
Powering
Cooling
Protecting of ICs
New Era: The SOP Era or Microsystems Era (2000-)

Interconnecting
Powering
Cooling
Protecting of All System Components & Their Integration
Slide 11 | 08-20-2015
3 Types of Systems Packaging Platforms

System Packaging Platforms
System-on-Chip
(SOC)
Continues for logic
Split-die on horizon
Cant integrate logic,
memory, RF, sensors,
analog
Slide 12 | 08-20-2015
System-on-Board
(SOB)
Current approach is
bulky, expensive
Future limits in
thickness and
functionality,
Board is biggest barrier
to system
miniaturization
System-on-Package
(SOP)
Most strategic, focus
on miniaturization and
integration
Two integration
platforms
1) Wafer-based
devices
2) Panel-based
modules
Module architectures
2D SCM & MCM
2.5D MCM
Si, glass, organics
3D MCM
GT Vision for System Scaling by 10-50X

1. ELECTRICAL MODELING
DESIGN AND TEST
2. MECHANICAL DESIGN FOR 3. NANO SCALE MATERIALS

RELIABILITY
AND PROCESSES
6. 3D Opto
3. 3D ThinPack
PD/TIA
LASER
PHOTODETECTOR
CHIP-LAST
EMBEDDED IC
Waveguide
NANOMAGNETICS
EBG &
Isolation
5. MEMS
Packaging
SENSORS
MEMS
Bio-Sensor
GaAs RFIC
THERMAL SOP
SYSTEM ON CHIP (SOC)
ANTENNAS &
FILTERS
50m
3D CAPACITORS
4. TPI
Glass or Si Core
30m
1. Glass Interposer
2. Low Cost Si
Interposer
7. SLI
HIGH DENSITY I/O
3D ICs
50m
POWER & BATTERIES
8. 3D Design Tools
and Architecture
4. THINFILM
PASSIVES
Slide 13 | 08-20-2015
5. THERMAL
TECHNOLOGIES
6.INTERCONNECTIONS,
ASSEMBLY & RELIABILITY
7. INTERPOSERS
AND PACKAGES
Chapter 2
Slide 14 | 08-20-2015
Difference between SIP, 3D ICs and SOP
Chip
ChipStacking
Stacking
Chip Stacking
(Non-TSV)
(Non-TSV)
(Non-TSV)
SIP
Stacked
ICs
Package
Package
Package
Stacking
StackingStacking
(Non-TSV)
(Non-TSV)
(Non-TSV) TSV
TSVChip/Wafer
Chip/Wafer
TSVICs
Chip/Wafer
Stacking
Stacking
SIP
Stacked
Packages
3D
withStacking
TSV
SIP Means Stacked ICs and Packages

(SIP)
Logic
Logic
Logic
IC
IC
IC
Chip Stacking (Non-TSV)
Package Stacking (Non-TSV)
Logic IC
SOP Platform
Slide 15 | 08-20-2015
TSV Chip/Wafer Stacking
Ultra-thin Electronics System Scaling

Technologies
2.5D and 3D Interposers

Silicon and Glass Interposers
Electrical Design
Thermal SOP
MEMS SOP
RF SOP
Opto SOP
Package Materials
Chip-Level Interconnections
Board-Level Interconnections
Organic Packages
Thinfilm Passive Components
Slide 16 | 08-20-2015
System-On-Package Technologies
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS
WAFER LEVEL PACKAGING AND ASSEMBLY

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
Si or GLASS INTERPOSER
POWER
MIXED SIGNAL DESIGN
Slide 17 | 08-20-2015
DESIGN FOR RELIABILITY
System on Chip (SOC)

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 18 | 08-20-2015
SIP and 3D ICs

SENSORS
SYSTEM-IN-PACKAGE
(SOP)
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 19 | 08-20-2015
Mixed Signal Design

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED
MIXEDSIGNAL
SIGNALDESIGN
DESIGN
Slide 20 | 08-20-2015
MEMS Packaging
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 21 | 08-20-2015
Antennas and Filters

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 22 | 08-20-2015
Optoelectronics
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
PD/TIA
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 23 | 08-20-2015
Thermal SOP
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 24 | 08-20-2015
2, 2.5D and 3D Interposers and Packages

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
POWER
MIXED SIGNAL DESIGN
Slide 25 | 08-20-2015
Nano Bio-Components
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 26 | 08-20-2015
Sensors
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 27 | 08-20-2015
Design for Reliability

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 28 | 08-20-2015
DESIGN
DESIGNFOR
FORRELIABILITY
RELIABILITY
1st Level
Chip-Package Interconnections
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 29 | 08-20-2015
2nd Level Interconnections

SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 30 | 08-20-2015
System-On-Package Technologies
SENSORS
3D ICs
MEMS PACKAGING
THERMAL SOP
OPTO SOP
Ga-As
MEMS

OPTOELECTRONICS
EMBEDDED COMPONENTS
ANTENNAS AND
FILTERS
POWER
MIXED SIGNAL DESIGN
Slide 31 | 08-20-2015
SCALING Research
Education
Slide 32 | 08-18-2015
NEW INDUSTRY-ACADEMIC
MODEL
Slide 33 | 08-20-2015
System Scaling Requires New Global

Academic-Industry-Govt. Model
Small & ultrasmall
Systems
System
Scaling
New
AcademicIndustry
Model
New Technologies
Skilled Resources
Global
End-User-to-Supply
Chain Mfg.
New Academic-Industry Collaboration Model
Slide 34 | 08-20-2015
Why Should Industry Collaborate with Academia?

Exploratory
Research
Strategic
Research
Technology
Development
Manufacturing
Traditional
Technology Transfer ~5%
Technical Scope
Corporate
Technology Transfer ~ 20%
Traditional
Academic
Research
Corporate
Research
Government Funding
Industry
Funding
Industry Manufacturing
GT PRC
Industry Consortia Funding
GT PRC
Technology Transfer ~ 50%
10
Slide 35 | 08-20-2015
3
Time in Years
The New Academic-Industry Model

System Fab
Facilities
Academic
Faculty
PRC
Staff
Graduate
Students
Research
Faculty
Engineers
on Campus
Industry
Partners
Slide 36 | 08-20-2015
Highly-Interdiscipline Faculty
System Fab
Facilities
Academic
Faculty
PRC
Staff
Interdisciplinary
Academic Faculty
Graduate
Students
Research
Faculty
Engineers
on Campus
Prof. Rao Tummala

Professor & Center Director
Industry
Partners
Prof. Farrokh Ayazi

MEMS
Prof. Maysam
Prof. GK Chang
Prof. Peter Hesketh
Plus
Ghovanloo
Sensors
Optomany more
Prof. Yogendra
Joshi
Thermal
Bioelectronics
Prof. Joungho Prof. Satish Kumar Prof. Suresh

Sitaraman
LED
Kim (KAIST)
Mechanical Design
Electrical Design
Prof. Madhavan
Prof. CP Wong
Swaminathan Polymer Materials
RF
Slide 37 | 08-20-2015
GT PRCS
GLOBAL INDUSTRY CONSORTIUM
To Stimulate Global Interest
Slide 38 | 08-20-2015
Research Strategy & Industry Programs

Core Technologies
1. Design
D&D Test Vehicles
2. Materials
3. Devices
Communication
Electronics
Electronics
Photonics
mm-Wave
Power Electronics
Sensor Electronics
4. Electronic Substrates
5. Photonic Substrates
6. High-temp Electronics
7. Power Electronics
8. Sensing Electronics
9. RF and mm-Wave Electronics
10. EMI Design & Materials
11. Interconnections & Assembly
Slide 39 | 08-20-2015
SubSystem
Integration
SOP
GT-PRC Industry Consortia Program

Application
End Users
Board
Assembly
(EMS)
Device
Manufacturers
Package
Integrators
(OSAT)
Material &
Tool Suppliers
Interposer
Manufacturers
Slide 40 | 08-20-2015
Single Industry Consortium with 10 Critical

System Scaling Technologies
Low-cost Organic
I&P (LOIP)
Low-cost 2.5D and

3D Glass I&P
(LGIP)
Low-cost 2.5D and

3D Silicon I&P
(LSIP)
2D
2D or
or 3D
3D IC
IC
Ultra-thin Actives
and Passives
(3D IPAC)
2D
2D or
or 3D
3D IC
IC
50m Pitch Organic

Packages
2X-10X Lower Cost &

10-50m I/O Pitch
2X-10X Lower Cost &

10-50m I/O Pitch
3D Glass Photonics
(3D GP)
Board-level
Interconnect,
Assembly &
Reliability (BLIAR)
10m Pitch
Off-chip
Interconnects
5X Thinner Than IPD

for Functional
Modules
Low Cost Glass

Package with TPV &
High Reliability
Electrical Design
for Power, Signal,
Noise & Bandwidth
Mechanical Design
for Warpage and
Reliability
IC
Si or Glass
BLIAR
PWB
Slide 41 | 08-20-2015
All-Glass MEMS
Packaging (with
CMMT Center)
GT PRC - Consortia Programs

& Program Managers or Faculty Leaders
1. Design
Dr. K. Panayappan
Electrical
2.5D Interposer for
bandwidth
Signal, power delivery, noise, X-talk
2. Electronic
Substrates
Dr. Venky Sundaram

Prof. GK Chang
Glass Substrates
3D Glass Photonics
3D Glass substrate Bandwidth beyond
@ @ 40m Pitch
TSV
2.5D Glass substrate @ 20m pitch
Prof. Suresh Sitaraman Prof. C.P. Wong

Mechanical
Polymer Materials
Warpage, reliability
High Temp.
Molding compounds
Prof. Yogendra Joshi

Thermal
Thermal
conductivity of glass
Thermal interfaces,
characterization
Slide 42 | 08-20-2015
3. Photonic
Substrates
Dr. Fuhan Liu

RDLs
< 2m lithography
< 6m microvia
4-6 layer RDL@
20-40m pitch
Prof. Stephen Ralph

Opto Electronic Mfg
Mfg. processes
Photonic structures
4. Functional
Components
5. High-power &
Dr. P.M. Raj

3D IPAC Functional
Components
3D Passive &
actives in less than
100m
Dr. Vanessa Smet

3D Digital, RF, mm- Low Temp I&A,
Double-side I&A
Wave Mixed Signal
Low-temp Cu at
Modules
20m pitch with and
High-temp modules
without solders
High-power
modules
3D Integrated
MEMS and sensors
Dr. Himani Sharma

3D IPAC Power
Modules
Capacitors and
inductors
Dr. Junki Min

3D IPAC RF Modules
Diplexers
LNA
Filters
EMI Shields
High-temp, Mixed
Function Electronics
Prof. Klaus Wolter
6. Interconnects &
Assembly
Building Bridges with Global Companies

UNITED STATES
Brewer Sci - Polymers
Corning Glass
Rogers Dielectrics
Applied Materials PVD,
CVD Tools
Coherent Laser
K&S TCB Bonder
MKS Plasma Etching
SSEC Cleaning
Tango PVD Tools
Amkor Assembly
QualiTau Assembly
Ciena Opto
Draper Labs User
Global Foundries
IBM High Perf.
Maxim Passives
Qualcomm All
TE Opto
TI Passives
Materials
Slide 43 | 08-20-2015
EUROPE
HC Starck Capacitors
Schott Glass
Atotech Plating
EVG Spray Coating
Suss Laser Via
Nanium Bumping
TDK-Epcos RF
CHINA
JCET Bumping
KOREA
UNID Materials
Fusei Menix Lamination
Gigalane RF
TAIWAN
Unimicron 2.5D
ASE Assembly
Quanta Assembly
TSMC User
Tools
Substrates
Assembly
JAPAN
Ajinomoto Dry Film
Asahi Glass Glass
Hitachi Chemical Photoresist
MGC Laminates
TOK Photopolymer
Zeon Dielectrics
Asahi Glass TPV
Disco Dicing
Mitsubishi Electric Laser
Ushio Lithography
NGK/NTK 2.5D
Shinko 2.5D
Namics Underfill
Users
SCALING
Research
Education
Slide 44 | 08-18-2015
Education Strategy
Inter-disciplinary
&
System
Education
Disciplinary
Education
Packaging Education
Slide 45 | 08-20-2015
Education Strategy
Disciplinary Education
VLSI Design
Semiconductor Devices
Microwave Design
Wireless IC Design
Analog Electronics
Nanoscale Devices
Gigascale Integration
MEMS
Radar and EM Sensing
Optoelectronics
Finite-Element
Functional Materials
Electro Optics
Nanomaterials and Structures
Slide 46 | 08-20-2015
Packaging and
System Level Education
Packaging Design
Package Substrates
Packaging Assembly
System Packaging
EMI Packaging
Hands-on Substrate
Fabrication
Hands-on Assembly
Bioelectronics
Power Electronics

Introduction to SOP Technologies

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ECE/ME/MSE 6776A

Introduction to SOP which includes

Educational Programs in SOP at GT

ECE/ME/MSE 6776 SOP by System Scaling

ECE/ME/MSE 6776 SOP by System Scaling

SOP BY SYSTEM SCALING

ECE/ME/MSE 6776 SOP by System Scaling

An Example of System Scaling vs.

System Scaling (I/O Pitch)

Courtesy: S.S. Iyer, IBM

ECE/ME/MSE 6776 SOP by System Scaling

Node dimension (nm)

Packaging to date: Single or Multiple ICs

3D ICs with TSV

Laser array (VCSEL)

ECE/ME/MSE 6776 SOP by System Scaling

Sources: Infineon, Georgia Tech, Stats, ST Ericsson

SOP is like SOC; instead of being on an IC, it is on a

ECE/ME/MSE 6776 SOP by System Scaling

Total System Miniaturization

Optimize for cost and performance between device &

ECE/ME/MSE 6776 SOP by System Scaling

PRC Vision of Digital Convergence by 1000X

ECE/ME/MSE 6776 SOP by System Scaling

Package is the System

System: Convergent Computing,

ECE/ME/MSE 6776 SOP by System Scaling

What is Packaging in the new Era?

Old Era: The SOC or Microelectronics Era (1965---)

New Era: The SOP Era or Microsystems Era (2000-)

ECE/ME/MSE 6776 SOP by System Scaling

3 Types of Systems Packaging Platforms

ECE/ME/MSE 6776 SOP by System Scaling

GT Vision for System Scaling by 10-50X

2. MECHANICAL DESIGN FOR 3. NANO SCALE MATERIALS

SYSTEM ON CHIP (SOC)

POWER & BATTERIES

ECE/ME/MSE 6776 SOP by System Scaling

ECE/ME/MSE 6776 SOP by System Scaling

Difference between SIP, 3D ICs and SOP

SIP Means Stacked ICs and Packages

Chip Stacking (Non-TSV)

Package Stacking (Non-TSV)

ECE/ME/MSE 6776 SOP by System Scaling

TSV Chip/Wafer Stacking

Ultra-thin Electronics System Scaling

2.5D and 3D Interposers

ECE/ME/MSE 6776 SOP by System Scaling

SYSTEM ON CHIP (SOC)

WAFER LEVEL PACKAGING AND ASSEMBLY

DESIGN FOR RELIABILITY

ECE/ME/MSE 6776 SOP by System Scaling

System on Chip (SOC)

SYSTEM ON CHIP (SOC)

WAFER LEVEL PACKAGING AND ASSEMBLY

DESIGN FOR RELIABILITY

ECE/ME/MSE 6776 SOP by System Scaling

SIP and 3D ICs

SYSTEM ON CHIP (SOC)

WAFER LEVEL PACKAGING AND ASSEMBLY

DESIGN FOR RELIABILITY

ECE/ME/MSE 6776 SOP by System Scaling