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11/11/15
EEPROM
SRAM
Multiplexors
Logic Block
Pin Assignment
Flash
High density
Process issues
RAM-based
Interconnect
direct
general-purpose
long lines of various lengths
RAM-programmable
can be reconfigured
IOB
CLB
CLB
IOB
IOB
Wiring Channels
IOB
CLB
IOB
IOB
IOB
IOB
CLB
Storage element
Latch or flip-flop
Set and reset
True or inverted inputs
Sync. or async. control
4-input
function
3-input
function;
registered
e.g. 9-input
parity
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
Look-Up tables
are primary
elements for
logic
implementation
Each LUT can
implement any
function of
4 inputs
x1 x2
y
y
COUT
YB
G4
G3
G2
G1
Y
Look-Up
Table O
Carry
&
Control
Logic
CK
EC
F5IN
BY
SR
XB
F4
F3
F2
F1
CIN
CLK
CE
X
Look-Up
Table O
Carry
&
Control
Logic
S
D
CK
EC
SLICE
x
0
0
1
1
y
0
1
0
1
COUT
x
y
CIN
CIN
Propagate = x y
Generate = y
Sum= Propagate CIN = x y CIN
LUT
Hardwired (fast) logic
Connection boxes
Flexibility of Connection, Fc = 2,
Can A connect to B?
Switch Boxes
Fs, defines for a wiring segment entering
the S block the number of other wiring
segments it can be connected to
Maze Router
A* Search Routing
The Pathfinder
Eight general-purpose
(active-High) DIP
switches are connected
to the user I/O pins of
the FPGA
Ethernet Port
10/100/1000 Mb/s
Audio Jacks for Microphone, Line In, Line Out,
and Headphone. Supports stereo 16-bit audio
with up to 48-kHz sampling
Allows for the utilization for the Base System Builder (BSB) if
required for development of an existing board including layout
and pin connections
The Base System Builder allows for the selection of the following system
attributes:
Processor type (MicroBlaze or PowerPC, depending on your selected target
FPGA device)
Reference and processor-bus clock frequency (BSB automatically infers and
configures a Digital Clock Manager (DCM) primitive when needed)
Standard processor buses (all peripherals are automatically connected via
appropriate buses)
Debug interface
Cache configuration
Memory size and type (both on-chip block RAM and controllers for off-chip
memory devices)
Common peripherals (such as general purpose I/O, Universal Asynchronous
Receiver-Transmitter (UART), and timer)
Automatic selection of the on-board FPGA
Selection of clock rates supported by the on-board oscillators
Automatic setting of reset polarity
Automatic generation of FPGA pinout to match the board connections, for the
selected set of peripherals