Lecture 6

Logic gates :
Power and Other Logic
Family
Pradondet Nilagupta
pom@ku.ac.th
Department of Computer Engineering
Kasetsart University

Acknowledgement
This

lecture note has been summarized from

lecture note on Introduction to VLSI Design,
VLSI Circuit Design all over the world. I cant
remember where those slide come from.
However, Id like to thank all professors who
create such a good work on those lecture
notes. Without those lectures, this slide cant
be finished.

Parasitics and Performance

Consider the following

layout:
What is the impact on
performance of
parasitics

At point a (VDD rail)?b

At point b (input)?
At Point c (output)?

Parasitics and Performance

a - power supply
connections

capacitance - no effect
on delay
resistance - increases
delay (see p. 135)
b
minimize by reducing
difffusion length
minimize using parallel
vias

Parasitics and Performance

b - gate input

capacitance increases
delay on previous stage
(often transistor gates
dominate)
resistance increases
b
delay on previous stage

Parasitics and Performance

c - gate output

resistance, capacitance
increase delay
Resistance &
capacitance "near" to
output causes additional
b
delay

Driving Large Loads

Off-chip loads, long wires, etc. have high capacitance

Increasing transistor size increases driving ability (and
speed), but in turn increases gate capacitance
Solution: stages of progressively larger transistors
Use nopt = ln(Cbig/Cg).

Scale by a factor of =e
pullup: W p /L p

pullup: W p /L p

pullup: W p /L p

pulldown: W n /L n

pulldown:

pulldown:

W n /L n

W n /L n

Cbig

n stages

Summary: Static CMOS

Advantages
High Noise Margins (V OH=VDD, VOL=Gnd)
No static power consumption (except for leakage)
Comparable rise and fall times (with proper sizing)
Robust and easy to use
Disadvantages
Large transistor counts (2N transistors for N inputs)
Larger area
More parasitic loading (2 transistor gates on each input)
Pullup issues
Lower driving capability of P transistors
Series connections especially problematic
Sizing helps, but increases loading on gate inputs

Alternatives to Static CMOS

Switch

Logic

nmos
Pseudo-nmos
Dynamic

Logic
Low-Power Gates

Switch Logic
Key

idea: use transistors as

switches
Concern: switches are
bidirectional
A

AND
A
B
OR
10

Switch Logic - Pass Transistors

Use

n-transistor as switches
Threshold problem
Transistor
VDD

IN:
VDD

switches off when Vgs < Vt

input -> VDD-Vt output

Special

OUT:
VDD-Vtn
A:
VDD

gate needed to restore

values

11

Switch Logic - Transmission

Gates
Complementary

transistors - n and p
No threshold problem
Cost: extra transistor, extra control
input
Not a perfect conductor!
A

A
12

Switch Logic Example - 2-1 MUX

SEL

IN1

OUT

SEL

IN

IN2

SEL

13

Charge Sharing

Consider transmission gates in series

Each node has parasitic capacitances
Problems occur when inputs change to redistribute
charge
Solution: design network so there is always a path
from VDD or Gnd to output
A

14

Aside: Transmission Gates in

Analog
Gates work
with analog values, too!
Example:
Voltage-Scaling D/A
Converter

S3

Transmission

S3
S2

S2
S1

S1
S0

OUT

S0

15

NMOS Logic

Used before CMOS was widely available

Uses only n transistors
Normal n transistors in pull-down
network
depletion-mode n transistor
(Vt < 0) used for pull-up
"ratioed logic" required
Tradeoffs:
+ Simpler processing
+ Smaller gates
- higher power!
- Additional design considerations
for ratioed logic

Passive Pullup Device:

depletion Mode
n-transistor (Vt < 0)
OUT
Pulldown
Network

16

Pseudo-nmos Logic

Same idea, as nmos, but use ptransistor for pullup

"ratioed logic" required for proper
design (more about this next)
Tradeoffs:
+ Fewer transistors -> smaller gates,
esp. for large number of inputs
+ less capacitative load on gates that
drive inputs
larger power consumption
less noise margin (VOL > 0)

Passive Pullup Device:

P-Transistor
OUT
Pulldown
Network

additional design considerations

due to ratioed logic

17

Ratioed Logic for Pseudo-nmos

Approach:
Assume VOUT=VOL =0.25*VDD

Idp

Assume 1 pulldown transistor is on

Equate currents in p, n transistors
Solve for ratio between sizes of p, n
transistors to get these conditions
Further calculations necessary for
series connections

OUT
Pulldown
Network

Idn

I dn I pn

Wp
2 1
1
Wn
2
k' n
Vgs,n Vtn k' p
2 Vgs,p Vtp Vds,p Vds,p
(EQ 3 21)
2
Ln
2
Lp

Wp
Wn

Lp
Ln

3.9 (EQ 3 22) Assu min g VDD 3.3V

18

DCVS Logic

DCVS - Differential Cascode Voltage

Switch
Differential inputs, outputs
Two pulldown networks
Tradeoffs
OUT
+

+
+
-

Lower capacitative loading

A
B
than static CMOS
C
No ratioed logic needed
Low static power consumption
More transistors
More signals to route between gates

OUT
Pulldown
Network

OUT

OUT
Pulldown
Network

A
B
C

Example: Fig. 3.29 p. 148

19

Dynamic Logic
Key

idea: Two-step operation

precharge

- charge CS to logic

high
evaluate - conditionally
discharge CS
Control

Storage Node
CS

Precharge
Signal Pulldown

- precharge clock

Network

Precharge

Evaluate

Precharge

Storage
Capacitance

20

Domino Logic
Key idea: dynamic gate + inverter
Cascaded gates - monotonically
increasing

CS

1
0
1
in4

x1

x2

x3

Pulldown
Network

B
C

in4
x1
x2

x3

21

Domino Logic Tradeoffs

+
+
-

Fewer transistors -> smaller gates

Lower power consumption than pseudo-nmos
Clocking required
Logic not complete (AND, OR, but no NOT)

22

More Techniques for Saving

Power

Reduce VDD (tradeoff: delay)

Multiple Power Supplies
High VDD for fast logic
Low VDD for slow logic
(level translation an issue)
DCSL - Fig. 3-35, p. 155
cross-coupled outputs
partially disconnected pulldown network
Dealing with leakage currents (p. 158)
Multiple-Threshold CMOS (MTCMOS) - Fig 3-37
Variable-Threshold CMOS (VTCMOS) - Fig 3-38
23

Delay in Long Wires - Lumped RC

Model

What is the delay in a long wire?

L

in

Lumped RC Model:
in

out

out
C

R = Rs * L / W = r*L
(r = Rs / W - resistance per unit length )
C = L * W * Cplate = c*L
(c = W * Cplate - capacitance per unit length)

Delay time constant (ignoring driving gate)

= R * C = (Rs * L / W) * (L * W * Cplate )
= r * c * L2
Problem: Overly Pessimistic

24

Delay in Long Wires Distributed RC Model

Alternative: Break wire into small segments

in

R 1 = rL

R 2 = rL

R n = rL

C1
cL

C2
cL

Cn
cL

out

Approx. Solution - 1st moment of impulse response

(Vout ) rcL 2

NN 1

rcL2
(Vout )
for N
2

Important: delay still grows as square of length

25

Delay in Long Wires Consequences in design

Distributed

in

Delay

RC model:
out

rcL2
(Vout )
2

grows as square of L!

Choose

wire material that minimizes r, c

Break wire into buffered segments to optimize
delay
in

out

26

Elmore Delay

Consider R-C ladder network with unequal values

R1

in

R2

C1

Ri

C2

Ci

Rn

out

Cn

First-order time constant at node N is

N

i1

ji

i 1

j1

N R i C j Ci R j

First-order time constant and node I is

i C1 R1 C2 ( R1 R2 ) ... Ci ( R1 R2 ... Ri )

27

Elmore Delay Applications

Wire

sizing to minimize delay

Delay prediction of complex networks
(as long as they take the form of a ladder)

28

Elmore Delay Homework Problem

What

are the Elmore time constants 1, 2, 3?

in

R1
100
C1
50fF

R2
50
C2
70fF

R3
200

out

C3
90fF

29

Wire Sizing

Recall distributed model of wire: multiple segments

R1

R2

Rn

in

out
C1

C2

Cn

i C1 R1 C2 ( R1 R2 ) ... Ci ( R1 R2 ... Ri )

note strong impact of R1, lesser impact of R2, etc

Idea: Reduce overall delay by tapering segments

Make Segment 1 widest to reduce R1 (increases C1)
Make Segment 2 less wide to reduce R2 (increses C2)
etc.
30

Wire Sizing
Ideal

Result wire should taper exponentially

- see Eq. 3-20, p. 163 [Fis95]:

More

pragmatic approach: step-tapered wire

[Fis95] J. Fishburn and C. Schevon, Shaping a distributed-RC line to minimize

Elmore delay, IEEE Trans. on Circuits and Systems-I, December 1995, pp. 1020-1022

31

Buffer Insertion

Key Idea: Break long wire up into stages (Sec. 3.7.3)

in

out

Equivalent Circuit: Fig. 3-44, p. 167

50% delay of each segment: Eq 3-35
Number of stages for minimum delay: Eq 3-36
Best size and number of stages: Eq 3-38 - 3-39

32

Wire Sizing - New Results

Alternative approach [Alpert01]:

Combine buffer insertion and
Untapered wires of (small number of) different widths
in

out

Theoretical result: Tapering gives at best 3.5%

improvement over this approach
Practical result: tapering generally not worthwhile

[Alpert01] Interconnect Synthesis without wire tapering, IEEE Trans. CAD, Vol. 20, No. 1, January 2001,
pp. 90-104

33

Delay in RC-Trees
Many

interconnection networks are trees

Extracted

RC circuit modeling a gate output

Clock trees
R2

R1
in

C2

R3

o1

C3

C1
R4
C4

R5
C5

R6

o2

C6

34

Delay in RC-Trees:
Penfield-Rubenstein Bounds

Key idea: characterize time constants in terms of

Path resistances between nodes
Capacitance values at each node

in

R ko R j (R j [path(in o) path(k o)])

R2
R3
2
3
o1
R1
1
C2
C3
C1
R4
C4

R5
C5

R6

o2

C6

35

Delay in RC-Trees:
Penfield-Rubenstein Bounds
Time

constants Tp, TDo, TRo (eqn. 3-30 - 3-34)

Table

3-2 (p. 165) - bounds for time, voltage

36