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Combination Logic
Design
Pradondet Nilagupta
pom@ku.ac.th
Department of Computer Engineering
Kasetsart University
Acknowledgement
This
Topics
Combinational
logic functions.
Static complementary logic gate structures.
Gate design
Why designing gates for logic functions is nontrivial:
may
f = ab + ab
a
Irredundancy
A
expressions:
a*b+a
a*b+a*b'
Irredundant
expressions:
a*b'+a'*b
a+c*d'
Completeness
A
Minimality
A
10
VDD
VDD
Pullup
Network
(p-transistors)
Inputs
Out
Pulldown
Network
(n-transistors)
Gnd
In
Out
Gnd
Inverter
11
Inverter layout
VDD
+
tub ties
out transistors
a
out
(tubs not
shown)
GND
12
B
C
OUT = (A*(B+C))
A
13
Layout Considerations
Metal
but
Do the analysis first to see if its necessary
14
necessary):
Metal
1
Metal 2
Poly
Diffusion
Specify
15
NAND gate
+
out
b
16
NAND layout
VDD
+
out
b
out tub
ties
b
a
GND
17
18
NOR gate
+
b
a
out
19
NOR layout
VDD
a
out
tub ties
b
out
a
GND
20
21
22
AOI/OAI gates
AOI
23
AOI example
out = [ab+c]:
invert
symbol
circuit
or
and
24
25
b
b
dummy
dummy
26
Inverter - DC Analysis
A
NMOS off
PMOS lin
B
NMOS sat
PMOS lin
Vou t
NMOS sat C
PMOS sat
out
in
NMOS lin
PMOS sat
NMOS lin
PMOS off E
Vin
27
Vout VDD
Vout
D
E
2
Vtp VDD n Vin v tn
Vin Vtp 2 2 Vin VDD
2
p
VDD
2
2
2 p
V
V
in tn Vin VDD v tp
n
Vout 0
Note dependence on n/ p
' Wp
Recall: k' Wn
p kp
n
Ln
Lp
Source: N. Weste & K. Eshraghian, Principles of CMOS VLSI Design Addison Wesley, 1992
28
Logic
Static
VOL
29
VIN < VIL small change in VIN causes small change in VOUT
VIN > VOUT small change in VIN causes small change in VOUT
VIN < VIL < VIH small change in VIN causes large change in VOUT
30
"1"
OH
V
IH
V(y)
Slope = -1
V
OH
Undefined
Region
"0"
V
IL
V
OL
Slope = -1
VOL
V
IL
IH
V(x)
31
Noise Margin
A
Logic
Logic
Important
Definition:
32
To balance noise
margin:
n
10
p
n
0.1
p
n
1
p
Vin
33
Gate Delay
Consider
RL
CL
34
Simplifying Assumptions
Assume
Vds
(See
123)
Use average of Vds/Id at:
middle
maximum
/ 2
I sat I lin
EQ 3 1
Vsat V DD VSS
I sat
1 W
2
k V DD VSS Vt
2 L
Vlin V DD VSS Vt / 2
W 1
2
1 VDD VSS Vt
Ilin k VDD VSS Vt
L 2
2
2
2
3 W
2
k V DD VSS Vt
8
L
36
VDD V SS
VDD VSS Vt / 2
/ 2
1 W
3 W
2
2
k VDD VSS Vt
k VDD VSS Vt
2
L
8 L
5 V 5 V 2 V
L 3 DD 3 SS 3 t
Rn
2
W k' VDD VSS Vt
37
38
CL
39
40
to Spice simulation:
Fig 3-19, p. 127
Estimate
41
series n-transistors
tf = 2.2 * (2 * Rn) * CL
Pullup:
parallel p-transistors
(worst case when one on)
tr = 2.2 * Rp * CL
V OUT
Rn
CL
Rn
42
parallel n-transistors
(worst case when one on)
tf = 2.2 * Rn * CL
Pullup:
series p-transistors
tr = 2.2 * (2 * Rp) * CL Rp
NOR
V OUT
CL
43
Gate Delay
Consider
VIN
VOUT
RL
CL
44
50%
50%
tpHL
Vout
tpLH
90%
50%
10%
50%
tf
tr
Delay: time to reach 50% of final value
tpHL (book calls this td)
tpLH
Transition Time: time between 10% and 90%:
tf - fall time
tr - rise time
45
Simplifying Assumptions
Assume
Use
middle
maximum
CL
Vss)
Book
Rp
Rn
46
/2
Isat Ilin
Vsat VDD VSS
EQ 31
1 ' W
2
Isat k n VDD VSS Vt
2 L
Vlin VDD VSS Vt /2
2
W 1
V Vt
2 1 V
Ilin kn VDD VSS Vt DD SS
L 2
2
2
3 W
2
kn VDD VSS Vt
8 L
47
/2
Isat Ilin
VDD VSS Vt /2
VDD VSS
/2
1 W
3 W
2
2
kn VDD VSS Vt
kn VDD VSS Vt
2 L
8 L
5
5
2
V V V
L 3 DD 3 SS 3 t
R n
W kn VDD VSS Vt 2
48
/2
Isat Ilin
EQ 31
kp VSS VDD Vt
8 L
49
/2
Isat Ilin
VSS VDD Vt /2
VSS VDD
/2
1 W
3 W
2
2
k VSS VDD Vt k VSS VDD Vt
2 L
8 L
5
5
2
V V V
L 3 SS 3 DD 3 t
R p
2
W k' VSS VDD Vt
50
VSS=0 to simplify:
5
2
V V
L 3 DD 3 t
R n
W kn VDD Vt 2
2
VDD Vt
L
3
3
R p
W kp VDD Vt 2
51
Example: Calculating Rn
Use
VDD 5V Vt 0.7V
kn 73A/V2 L 2 W 3
5
2
VDD Vt
L
3
R n 3
W kV V 2
n DD t
2
(5V) (0.7V)
2
3
3
14K
2
3 kn 5V 0.7V
52
Example: Calculating Rp
Use
2
VDD Vt
L
3
3
R p
2
W kp V
DD Vt
5
2
(5V) (0.8V)
2
3
3
14K
2
2
3 (21A/V )5V (0.8V)
53
type
Rn
Rp
VDD=5V
VDD=3.3V
3.9K
14K
6.8K
25K
54
t
(R n R L )C L
EQ 3 6
Rp
V DD
t pHL
0.5VDD VDDe
(R n R L )C L
RL
EQ 3 7 *
t 90%
t 10%
CL
Rn
55
t pHL
(R
R
)C
0.5VDD VDD 1 e n L L
Rp
V DD
RL
t 10%
t 90%
CL
Rn
56
tf = 2*2.2(Rn+RL)CL
Rp
Rp
RL
Rise
time: 1 p-transistor on
(for worst case)
tf = 2*2.2(Rn+RL)CL
CL
Rn
Rn
57
Rp
tf = 2.2(Rn+RL)CL
Rp
Rise
tf = 2*2.2(Rn+RL)CL
Rn
Rn
58
B
A
C
RL
CL
A
D
B
59
tf
CL (VDD VSS )
CL (VDD VSS )
(EQ 310)
2
Id
0.5kn W /LVDD VSS Vt
tr
CL (VDD VSS )
CL (VDD VSS )
2
Id
0.5kp W /LVSS VDD Vt
Fitted model
Measure several circuit characteristics & fit to formula
60
Accuracy of methods
Comparison
133
Model
Current Source Model
What
Use
to do:
simple models for
Quick
prediction of delay
Insight into circuit operation
Comparison of different circuits
Use
IN
OUT
C INV
C gp
CL
C INV
C gn
C INV
62
C =
gn
C gp
CINV=
CL=
C INV
C gn
0.675fF
63
t f=
83.61ps
64
Rise
time tr:
15
in series
A
B
C
C L=50fF
Fall
time t :
B
tf= 2.2 (2 f R n ) C L
15
Worst
series
connection
2.2 case:
(2 3.9K)
50 10
F
0.86ns
65
Increase
current
Reduce effective resistance (R n or Rp)
Side-effect:
R n(W3)
2
WNEW kn VDD Vt WNEW
3
R p(WNEW)
R p(W3)
WNEW
66
R n( W3)
3.9k
R p(W 31)
3
1.46k
8
R n( W3)
14k
3
8
W=31
L=2
3
31
3
1.35k
31
OUT
A
W=8
L=2
C L=20fF
t f 2.2 R
n(W 8) C L
2.2 1.46k 20fF 0.064ns
t f 2.2 (2 R p( W31) ) C L
2.2 2 1.35k 20fF 0.12ns
67
Make
Wp approximately 3.5*Wn
W=10
L=2
VIN
VOUT
W=3
L=2
68
B
C
36
18
A
36
3
B 6
C 6
69
To Pullup Network
OUT
T1
T2
CL
C1
+
V C1 =V sb1
-
V sb2 =0V
70
Body Effect
71
Power Consumption
Capacitor
Current,
Capacitor
Current,
73
P = f*CL*(VDD-VSS)2 = f*CL*VDD2
Where
f
overall chip:
P = f*CL*(VDD-VSS)2 = f*CL*VDD2
74
P' V '
2
DD
DD
P
5V
2.29
P' 3.3V
2
DD
P
5V
EXAMPLE : if V 5V, V ' 1.8V
7.72
P' 1.8V
2
DD
DD
75
so
'
'
'
t
R p VDD
VDD
r
Rp
VDD
t'r
5V
EXAMPLE : if VDD 5V,VDD' 3.3V
1.52
t r 3.3V
t'r
5V
EXAMPLE : if VDD 5V,VDD ' 1.8V
2.77
t r 1.8V
Tradeoff:
77
Speed-Power Product
A
DD
Bottom
78