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Outline
Motivation
Problem Statement
Background
Proposed Technique
Results
Conclusion
Jan 4-8, 2008
Motivation
Leakage power has become a dominant contributor to
the total power consumption
too leaky
too slow
0.45
P ro b a b ility
0.40
0.35
0.30
Delay
variation
(meannominal)/
nominal
STD /
mean
10%
-0.05%
0.65%
20%
-0.07%
1.12%
30%
-0.16%
1.50%
Leff
variation
(meannominal)/
nominal
STD /
mean
10%
3.10%
6.1%
20%
8.75%
30.7%
30%
25.17%
112.9%
0.25
0.20
0.15
0.10
0.05
0.00
Probability
Nominal
0.40
Probability
0.30
0.20
0.10
Nominal
0.00
Probability
Minimum leakage
Glitch elimination
Overall delay specification
Lu and Agrawal, CMOS Leakage and Glitch Minimization
for Power-Performance Tradeoff, JOLPE, vol. 2, no. 3,
pp. 1-10, December 2006.
Lu and Agrawal, Statistical Leakage and Timing
Optimization for Submicron Process Variation, Proc. 20th
Int. Conf. VLSI Design, Jan. 2007, pp. 439-444.
Hazard Filtering
(Gate/Transistor Sizing)
Path Balancing
1 3
1.5
2 0.5
Glitch Elimination
For every gate i:
Without process variation: | Ti ti | Di
With process variation: Prob{ | Ti ti | Di }
Inertial delay
Di
10
MILP Formulation
(Deterministic vs. Statistical)
Deterministic Approach
Statistical Approach
Basic MILP
Basic MILP
subnom ,i
i gate number
Minimize
subnom ,i
i gate number
11
k PO
Timing
window
Ti - ti
di <= Ti-ti
with glitch
di = Ti-ti
di <= Ti-ti
with glitch
Timing
window
Ti - ti
di >= Ti-ti
glitch free
di >= Ti-ti
glitch free
Gate delay di
Gate delay di
12
Timing
window
Ti - ti
di <= Ti-ti
with glitch
di = Ti-ti
di <= Ti-ti
with glitch
Timing
window
Ti - ti
di >= Ti-ti
glitch free
di >= Ti-ti
glitch free
Gate delay di
Gate delay di
13
Gate delay di
Di 3 Di ( Ti 3 Ti ) ( ti 3 ti )
14
0.30
0.20
0.10
0.00
statistical
Dynamic Power
(logic simulation)
Subthreshold Leakage
(Spice simulation)
0.20
Probability
Probability
0.40
0.15
0.10
0.05
0.00
Normalized Leakage
15
(-N2)/N2=15.22%
Conclusion
Circuits optimized of glitch suppression can
be seriously degraded by process variation.
Overdesign (3 variation) may reduce
sensitivity to process variation.
Statistical design (specified yields) can give
improved tradeoffs between leakage power,
glitch power and timing.
17
Future Work
Iterative MILP
for dual-Vth design
gate delay
= 2
8.2ns = 2
3.2
7ns
FF
8ns
LVT design
dual-Vthdesign
3
FF
18
19