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Acknowledgement
This
Overview
CMOS Processing & Fabrication
Components: Transistors, Wires, & Parasitics
Design Rules & Layout
Combinational Circuit Design & Layout
Sequential Circuit Design & Layout
Standard-Cell Design with CAD Tools
Systems Design using Verilog HDL
Design Project: Complete Chip
3
Determine placement of
layout objects
Color coding specifies
layers
Layout objects:
Rectangles
Polygons
Arbitrary shapes
Grid types
Absolute (micron)
Scaleable (lambda)
P substrate
n well
wafer
Mask Generation
Key idea:
Reduce layers to those that describe design
Generate physical layers as needed
Magic Layout Editor: "Abstract Layers
metal1 (blue) - 1st layer metal (equiv. to physical layer)
Poly (red) - polysilicon (equivalent to physical layer)
ndiff (green) - n diffusion (combination of active, nselect)
ntranistor (green/red crosshatch) - combined poly, ndiff
pdiff (brown) - p diffusion (combination of active, pselect)
ptransistor (brown/red crosshatch) - combined poly, pdiff
contacts: combine layers, cut mask
About Magic
Scalable
distance: lambda)
Value is process-dependent:
= 0.5 X minimum transistor length
Grid
Painting
metaphor
Paint
(red)
N Diffusion (green)
P Diffusion (brown)
Metal (blue)
Metal 2 (purple)
Well (cross-hatching)
Contacts (X)
Magic User-Interface
Cursor
Command window
(not shown)
Paint
(ntransistor)
Paint
(pdiff)
10
p-transistor
metal1
nwell
polycontact
pdc
metal1
poly
polycontact
poly
metal1
psc
ndc
ndc
ntransistor
11
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Manufacturing problems
Photoresist
shrinkage, tearing.
Variations in material deposition.
Variations in temperature.
Variations in oxide thickness.
Impurities.
Variations between lots.
Variations across a wafer.
13
Transistor problems
Varaiations
in threshold voltage:
oxide
thickness;
ion implanatation;
poly variations.
Changes
14
Wiring problems
Diffusion:
15
Oxide problems
Variations
in height.
Lack of planarity -> step coverage.
metal 2
metal 2
metal 1
16
Via problems
Via
17
18
19
Design Rules
Typical rules:
Minumum size
Minimum spacing
Alignment / overlap
Composition
Negative features
20
to be Scalable
Original
rules: SCMOS
Submicron: SCMOS-SUBM
Deep Submicron: SCMOS-DEEP
Pictorial
22
Contacts (Vias)
Cut size: exactly 2 X 2
Cut separation: minimum 2
Overlap: min 1 in all directions
Magic approach: Symbolic contact layer min. size 4 X 4
Contacts cannot stack (i.e., metal2/metal1/poly)
Other rules
cut to poly must be 3 from other poly
cut to diff must be 3 from other diff
metal2/metal1 contact cannot be directly over poly
negative features must be at least 2 in size
CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal
24
Design violations
displayed as error paint
Find which rule is
violated with ":drc
why
Polymustoverhang
transistorbyat
least2(MOSISrule
#3.3)
25
26
28
Layout Considerations
Break
Key
wires
goals:
Minimize
Hierarchy in Layout
Chips
Leaf
- hypothetical UART
Pad
register
FSM
Other
cells
30
Hierarchy Example
Root
Cell: UART
Root Cell:
UART
Pad
Frame
Pad 1
Pad 2
Core
...
Pad N
Shift
Register
FSM
Other
Cells
31
Wires
metal 3
metal 2
metal 1
pdiff/ndiff
poly
32
Transistors
2
3
2
3
1
33
Vias
Types
4
1
2
34
Metal 3 via
Type:
metal3/metal2.
Rules:
cut:
3x3
overlap by metal2: 1
minimum spacing: 3
minimum spacing to via1: 2
35
Tub tie
4
1
36
Spacings
Diffusion/diffusion:
Poly/poly:
2
Poly/diffusion: 1
Via/via: 2
Metal1/metal1: 3
Metal2/metal2: 4
Metal3/metal3: 4
37
Overglass
Cut
in passivation layer.
Minimum bonding pad: 100 m.
Pad overlap of glass opening: 6
Minimum pad spacing to unrelated metal2/3:
30
Minimum pad spacing to unrelated metal1,
poly, active: 15
38
39
placement of transistors
assignment of signals to layers
connections between cells
cell hierarchy
40
Layers
Metal (BLUE)
Connection Rules
poly n-diff p-diff metal
NC
X
S
NC
NC
S
41
Circuit Diagram.
Pull-Down Network
(The easy part!)
42
Vdd
Vdd
A
In
Out
Gnd
Out
Gnd
Inverter
NAND Gate
43
in
out
VSS
phi
phi
44
Out
B
A
Out
A
B
Gnd
B
Exclusive OR Gate
45
Gnd
Vdd
Out
Gnd
NAND Cell
Stick Diagram
Vdd
A
B
Vdd
NAND
Gnd
Out
Gnd
NAND Cell
Outline
46
47
cut:
Vdd
A
Vdd Vdd
A
Out
A
S
NAND
B
Gnd Gnd
Out
OUT
B
S
B
OUT = A*S + B*S
Vdd Vdd
A
Vdd Vdd
A
NAND
Out
B
Gnd Gnd
Out
S
Gnd
NAND
B
Gnd Gnd
48
49
NAND sticks
VDD
a
out
VSS
50
select
Vdd Vdd
Vdd Vdd
Vdd Vdd
Out
NAND
Gnd
B
Gnd Gnd
Out
NAND
B
Gnd Gnd
Out
NAND
Out
B
Gnd Gnd
51
a1
b1
a0
b0
ai
bi
ai
bi
ai
bi
select
select
select
m2(one-bit-mux)
select
select
m2(one-bit-mux)
select
select
m2(one-bit-mux)
VDD
oi
VSS
o2
VDD
oi
VSS
o1
VDD
oi
VSS
o0
52
Multiple-Bit Mux
select
Vdd
A0
A0
select
Vdd Vdd
Vdd Vdd
Vdd Vdd
Out
NAND
Gnd
Vdd
A1
B1
NAND
Out
NAND
B
Gnd Gnd
B
Gnd Gnd
B
Gnd Gnd
Vdd Vdd
Vdd Vdd
Vdd Vdd
Out
NAND
Gnd
Out
B
Gnd Gnd
Out
NAND
B
Gnd Gnd
Out
NAND
Out0
Out1
B
Gnd Gnd
53
Vdd Vdd
Vdd Vdd
Vdd Vdd
Out
NAND
Gnd
B
Gnd Gnd
Out
NAND
B
Gnd Gnd
Out
NAND
B
Gnd Gnd
B1
A1
Vdd
54
minimum-size transistors
Assume power supply lines pass through cell
from left to right at top and bottom of cell
Assume inputs are on left side of cell
Assume output is on right side of cell
Optimize cell to minimize width
Optimize cell to minimize overall area
55
Layout Example
Vdd!
Vdd!
OUT
Circuit Diagram.
B
Gnd!
Gnd!
Exterior of Cell
56
Overall Layout: 52 X 16
57
Architecture
Register-Transfer
Logic
Circuit
Layout
58
Circuit
Logic
59
60
Editors
Design Rule Checkers (DRC)
Circuit Extractors
Layout vs. Schematic (LVS) Comparators
Automatic Layout Tools
Layout
Generators
ASIC: Place/Route for Standard Cells, Gate
Arrays
61
Layout Editors
Goal:
description:
Absolute
63
Circuit Extractors
Goal:
Identify
active components
Identify parasitic components
Capacitors
Resistors
64
Compare
65
Simple:
Standard
cutters"
Gate Arrays - configurable pre-manufactured gates
(only change metal masks)
FPGAs - electrically configurable array of gates
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Automatic layout
Cell
68
routing area
routing area
routing area
routing area
69