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Abstract
Merging single bit flip-flops into one multi-bit flip-flop avoids duplicate
inverters, lowers the total clock power consumption and reduces the total
area.
Abstract
A combination table which can store the flip-flops that can be merged to
obtain a multi-bit flip-flop.
OBJECTIVES
To implement the sequential 8 bit ripple carry adder by using multi bit flipflop based highest 1s bit algorithm and to reduced the Flip-flop clock
power, delay and area.
LITERATURE SURVEY
TITLE
WORK DONE
This paper introduces a novel This paper minimize the Flipplacement flow with clock-tree
Flop power and Clock
aware flip-flop merging and
latency
when applying
MBFF generation, and
Multi-Flip-Flop only during
proposes the corresponding
placement.
algorithms to simultaneously
minimize flip-flop power and
clock latency when applying
MBFFs during placement.
[2].
Clock-Tree
Power This paper introduces an
Optimization based on RTL approach for reducing
Clock Gating
clock power based on clock
gating.
The power savings achieved ,
when the size of the circuits is
significant, savings on the power
consumption of the clock tree
are up to 75% larger than those
achieved by applying traditional
clock gating at the clock inputs
of the RTL modules of the
designs.
DISADVANTAGE
TITLE
WORK DONE
DISADVANTAGE
[3]. A Noble Research on to The multi bit flip-flop technique This paper designed the single
Reduce Clock Power by Using is one of the techniques used to
bit flip-flop to multi bit flipMulti Bit Flip Flops
reduce the clock power. The
flop transformation .but they
power reduction is
are not implemented any
achieved through the merging of
Logic circuits for analysis
flip-flops based on certain timing
performance
constraints
[4]. A Reduced Clock-Swing This paper introduces an
Flip-Flop (RCSFF) for 63% RCSFF can reduce the clock
Power Reduction
system power of a VLSI down
to one-third compared to the
conventional flip-flop and it can
reduced area, delay and power
TITLE
WORK DONE
DISADVANTAGE
EXISITNG SYSTEM
In existing system, they are only designed the Multibit Flipflop to reduced
the duplicate inverter compared from single bit flip-flop.
To Analysis and compared the single bit and multi bit flip-flop power
consumption.
Proposed System
In the proposed work used D-FF this makes low power when compared to other FF
and the output will be easy to processed. After finding that number the particular
bits of FF storage is getting enabled and remaining will be in sleep mode. It reduces
the power consumption and wire length for the MBFF.
Depends upon the FF storage enabled. The combination table is selected for FF
selection. [below Fig shows the single bit flipflop to multi bit flipflop
transformation].
To analysis the clock power and area consumption of single, two, four and eight
bit flipflop based adder design.
Block Diagram
Addition Waveform
The above figure shows the FPGA interfacing with LEDs and these LEDs
are used to find the added output
One end of the LED connected with FPGA and another end connected with
resistor
If the high value (1) comes to LED means light will glow otherwise (0)
it will not glow
The above diagram shows the interfacing LCD module with FPGA board
Typically LCD module has three control terminal and eight data terminal
The three control terminals are EN,R/W and RS and these are used to
control the LCD module
This LCD module used to shows the added value as well as find the
selection of flip flop
Working of hardware
In the hardware section we have two eight bit switches, these switches are
used to give the input to the adder
The LCD module shows the output according to the highest 1 bit
algorithm
Step 1 : Give 8 bit input through the 8 switch connected with FPGA board
Step 2 : Give another 8 bit input through the 8 switch connected with
FPGA board
Step 4 : The result can view in LCD module and also onboard LED light
Step 5 : If the MSB of output is binary 1 means the MSB will be stored
in
Step 6 : If the fourth bit of the output is 1 and before the fourth bit all 0
means 4 bit value only stored in 4 bit FF
The adder logic circuit is implemented in Xilinx FPGA and analysis the
clock power and area consumption of the logic circuit.
Hardware/Software requirement
Processor
Family
Series
Software
Simulation
Power analysis Tool
: FPGA
: Spartan 3E
: XC3S100 E VQG100C
: Xilinx ISE 12.4I
: ISE Simulator
: Xpower analysis
Conclusion
In this paper, we have introduced a new placement flow with clock-tree aware flipflop merging and MBFF generation. We have also proposed the corresponding
algorithms to simultaneously minimize power and clock latency when applying
MBFFs during placement and we also designed multiple bit Flip-Flop up to eight
bit and we are used that Flip-Flop for storing the output of eight bit adder. We have
showed the power comparison for single bit, two bit, four bit and eight bit Flip-Flop
with eight bit adder using Xilinx 12.4i software. Finally we have implemented this
adder in Spartan - 3E FPGA board.
Reference
Thank You