Architectural Analysis of a DSP

Device,
the Instruction Set and the Addressing
Modes
SYSC5603 (ELG6163) Digital Signal Processing
Microprocessors, Software and Applications
Miodrag Bolic

Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
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ADSP -21x

Copied from [Kester03]

CALCULATING OUTPUTS OF 4-TAP FIR

FILTER USING A CIRCULAR BUFFER
Memory
Location

Read

Write

Read

x(0)

x(4)

x(4)

x(1)

x(1)

x(2)

x(2)

x(2)

x(3)

x(3)

x(3)

y(3) =
y(4) =

Write

Read
x(4)

x(5)

x(5)

h(0) x(3) + h(1) x(2) + h(2) x(1) + h(3) x(0)

h(0) x(4) + h(1) x(3) + h(2) x(2) + h(3) x(1)

y(5) = h(0) x(5) + h(1) x(4) + h(2) x(3) + h(3) x(2)

Copied from [Kester03]

FIR filter steps

1. Obtain a sample with the ADC; generate an interrupt
2. Detect and manage the interrupt
3. Move the sample into the input signal's circular buffer
4. Update the pointer for the input signal's circular buffer
5. Zero the accumulator
6. Control the loop through each of the coefficients
7. Fetch the coefficient from the coefficient's circular buffer
8. Update the pointer for the coefficient's circular buffer
9. Fetch the sample from the input signal's circular buffer
10. Update the pointer for the input signal's circular buffer
11. Multiply the coefficient by the sample
12. Add the product to the accumulator
13. Move the output sample (accumulator) to a holding buffer
14. Move the output sample from the holding buffer to the DAC
Copied from [Kester03]

FIR filter steps (cont.)

ADSP21xx Example code:

Single
Cycle
Instruction

CNTR = N-1;
DO convolution UNTIL CE;
convolution:
MR = MR + MX0 * MY0(SS), MX0 = DM(I0,M1), MY0 = PM(I4,M5);

Copied from [Kester03]

Outline

FIR filter on ADPS-21x

DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization

Copied from [Takala05]

Copied from [Takala05]

Motorola DSP5600X

Copied from [Takala05]

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Copied from [Takala05]

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Copied from [Takala05]

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ADSP -21x
MAC

www.analog.com/dsp

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Copied from [Takala05]

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SHARC Architecture ADSP-2106X

Copied from [Takala05]

15

Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
16

Copied from [Takala05]

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Copied from [Takala05]

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Copied from [Takala05]

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Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
20

Copied from [Takala05]

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Copied from [Takala05]

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Hardware loops
Software loop:
LOOP:

MOVE #16,B
MAC (R0)+,(R4)+,A

Initialize loop counter B

Register-indirect addressing
with post-increment

DEC B
JNE
LOOP

Hardware loops: no time is spent on

Decrementing counters
Checking to see if the loop is finished
Branching back to the top of the loop
RPT #16
MAC (R0)+,(R4)+,A

[Lapsley97]

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Copied from [Kester03]

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Performance

ADI General Purpose DSP Product Families

Upto 160MMACS
Wired Voice
Wireless Voice
VOIP/VON
Industrial Control

Upto 4800MMACS (16-bit)

or 1200MMACS (32-bit)
TigerSHARC 2.5G/3G Infrastructure
High-Performance Medical Imaging
Industrial Imaging
$35 - $200
Multiprocessing

Blackfin
SHARC
Media Enabled
Low-Cost
$5 - $30
Floating Point
ADSP-218x/9x
$10 - $100
Power Efficient Upto 3000MMACS
Image compression
$5 - $10

Upto 600MMACS (32-bit)

Audio
Infotainment
Industrial

Digital Still/Video Camera

MMOIP
Telematics
Biometrics

www.analog.com/dsp

25

Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
26

SHARC Architecture

Copied from [Smith97]

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SHARC Architecture - Features

The Super Harvard ARChitecture
ARC

100MHz Core / 300 MFLOPS Peak

Parallel Operation of: Multiplier, ALU, 2 Address Generators &
Sequencer
No Arithmetic Pipeline; All Computations Are Single-Cycle

High Precision and Extended Dynamic Range

32/40-Bit IEEE Floating-Point Math
32-Bit Fixed-Point MACs with 64-Bit Product & 80-Bit Accumulation

Single-Cycle Transfers with Dual-Ported Memory Structures

Supported by Cache Memory and Enhanced HarvardArchitecture

Glueless Multiprocessing Features

JTAG Test and Emulation Port
DMA Controller, Serial Ports, Link Ports, External Bus, SDRAM
Controller, Timers

www.analog.com/dsp

28

ADSP-2106x Core Architecture

CACHE
MEMORY
32 x 48

DAG 1
8 x 4 x 32

JTAG TEST &

EMULATION
FLAGS

DAG 2
8 x 4 x 24

PROGRAM
SEQUENCER

PMA BUS

TIMER

24
PMA

DMA BUS

32
DMA

PMD BUS

48

DMD BUS

40

PMD

BUS CONNECT

FLOATING & FIXED-POINT

MULTIPLIER,
FIXED-POINT
ACCUMULATOR

www.analog.com/dsp

DMD

REGISTER
FILE
16 x 40

32-BIT
BARREL
SHIFTER

FLOATING-POINT
& FIXED-POINT
ALU

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Example- Dot product

C code

Copied from [Smith97]

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Example- Dot product - Assembly

Copied from [Smith97]

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Example- Dot product - Assembly

Copied from [Smith97]

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C or Assembly

How complicated is the program?

Are you pushing the maximum speed of the DSP?
How many programmers will be working together?
Which is more important, product cost or development
cost?
What is your background?
What does the DSP's manufacturer suggest you use?

Copied from [Smith97]

33

Outline
FIR filter on ADPS-21x
DSP Requirements
Fast Multiply-Accumulates (Data-path)
Extended Precision Accumulator Register (Data-path)
Dual Operand Fetch (Memory)
Circular Buffering (Addressing)
Zero-Overhead Looping (Instruction set)
Analog Devices Architectures and Programming
SHARC
Blackfin
Performance Optimization
34

BLACKfin Processor Core

Two 16-bit Multipliers

Two 40-bit ALUs, Four 8-bit Video ALUs
Barrel Shifter
Sixteen 16-bit /Eight 32-bit Math Registers

Address Arithmetic Unit

SP
FP
P5
P4
P3
P2
P1
P0

L3
L2
L1
L0

I3
I2
I1
I0

B3
B2
B1
B0

M3
M2
M1
M0

Two DAGs, byte addressing

Eight 32-bit pointer registers
Four Sets of 32-bit Index, Modify, Length, Base
16-bit Instructions, 32-bit Instructions
Multi-Issue, 64-bit Instructions
Interlocked Pipeline
Micro Signal Architecture, developed with Intel

DAG0

DAG1

Sequencer
R7
R6
R5
R4
R3
R2
R1
R0

8
Barrel
Shifter

16

40
Acc0

16

40
Acc1

Data Arithmetic Unit

www.analog.com/dsp

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ADSP-BF535 BLACKfin Processor

Architecture
Great Performance Value
Highest Frequency (350
MHz)
1.0V to 1.6V
260 PBGA
High System Integration
Address range 768Mbytes
SPORTs support 8
Channels of I2S Audio
(532Mbps) I/O Bandwidth,
DMA Bandwidth & Memory
Bandwidth
Microcontroller features
include WDT, PCI, USB1.1
SDRAM controller

Dynamic
Power
Management
PLL

To 350 MHz
BLACKfin
Processor Core

USB 1.1
SPORTs 2
SPI

Watchdog

JTAG

UART 2

Real Time
Clock

Timers 3 (32bit)

Interfaces

Memory
308
Kbytes
On-Chip
SRAM

48
Kbytes
On-Chip
Cache

264Kbytes
On-Chip
SRAM

GPIO 16
PCI

FLASH/SRAM
SDRAM

www.analog.com/dsp

User Peripherals

System Peripherals

DMA

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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Seminars about Blackfin

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