Chp7 CountersRegisters Part1

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Chp 7 Counters & Registers
Content
1.
Introductory Concepts
2.
Numbering Systems
3.
Boolean Algebra
4.
Combinational Logic
5.
Flip-Flops
6.
Digital Arithmetic
7. Counters & Registers Part 1

8.
IC Logic Families
9.
MSI Logic Circuits
Counters & Registers - Part 1

1.
Asynchronous (ripple) Counters
2.
Counters with MOD number < 2N
3.
IC Asynchronous Counters
4.
Asynchronous Down Counter
5.
Propagation Delay in Ripple Counters
6.
Decoding a Counter
7.
Decoding Glitches
8.
IC Registers
Counter?
Counter ?
output
reset
input
preset
max count
Revision
J K F/F (Revision)
J K
0 0
A
A0
0 1
1 0
0
1
(No change)
(Clear)
(Set)
A0
(Toggle)
J
CLK
JK F/F using it to build a counter
J K F/F -- to use it to build a counter

J K
0 0
A
A0
0 1
1 0
0
1
(No change)
(Clear)
(Set)
A0
(Toggle)
CLK
J & K must be
set to Toggle
mode
JK F/F using it to build a counter
J K F/F -- to use it to build a counter

1
J K
0 0
A
A0
0 1
1 0
0
1
(No change)
(Clear)
(Set)
A0
(Toggle)
preset
A
J
CLK
clear
1
Preset and Clear
must be set to inactive
Mod 2 counter
J K F/F - - how does it work as a counter?

1
CLK
CLK
1 0
The count goes 0, 1, 0 , 1

i.e. max count = 1
The cycle repeats after every 2 states

This is a called a mod 2 counter
Mod 2 counter building on - 1
How do we make it count more than 1?

Cascade the JK F/F (connect output to the next CLK)
B
CLK
CLK
B
3
A
4
K
7
All J, K, preset, clear = 1

8
CLK
Cont on Next slide
MSB
LSB
CLK
B
1
CLK
K
3
Where the clock is fed

that output is the LSB
K
7
All J and K inputs = 1

8
Max count =?
CLK
Number of states
in a cycle =?
LSB
A
Mod number =?
MSB
B
00 01 10 11
00 01
...
00 01 10 11
10
MSB
LSB
CLK
B
1
CLK
K
3
K
7
All J and K inputs = 1

8
Max count = 3
CLK
Number of
states in a
cycle = 4
LSB
A
MSB
B
00 01 10 11
00 01
...
Mod number =
4
00 01 10 11
11
7.1 Asynchronous Counters
Another e.g.
Guess, what is the mod number of this counter?
D
CLK
CLK
CLK
J
CLK
All J, K, preset, clear = 1
12
Where is the LSB and where is the MSB?

LSB
MSB
D
CLK
CLK
CLK
J
CLK
13
7.1 Asynchronous counters
Obtain the Counter - waveform

1
10
11
12
13
14
15
16
17
CLK
LSB
MSB
D
0000
0010
0001
0100
0011
0110
0101
1000
0111
1010
1001
1100
1011
1110
1101
0000**
1111
14
In the previous e.g.

Mod number = 16 which is 24
Where 4 is the number of FFs
i.e. The counter has 16 states, it counts from
0 to 24-1 (or 0 to 15)
15
The counters in our examples are ALL

Asynchoronous (Ripple) counters
In Asynchoronous counters,
Each FF output drives the CLK input of the next FF
16
Asynchoronous (ripple) counters

vs
Synchoronous counters
Asynchoronous Each FF output drives the
CLK input of the next FF
Synchoronous The same CLK input
drives all the FF
17
Defining MOD number ?

MOD number is the number of states the counter
goes through in each complete cycle.
18
Mod Number & Number of Flip Flops
1-bit
counter
2-bit
counter
3-bit
counter
4-bit
counter
Number of F/F
(N)
Mod number
(2N)
Max Count
(2N - 1)
16
15
19
What would the MOD number of the

counter be if three more FFs were added?
CLK
CLK
CLK
J
CLK
20
What would the MOD number of the

counter be if three more FFs were added?
CLK
CLK
CLK
J
CLK
Ans: 27=128
21
How many FFs are required to build a

counter that can count as many as 100010?
22
How many FFs are required to build a counter

that can count as many as 100010?
Applying Max Count formula
2N - 1 = 1000
2N = 1001
N log 2 = log 1001
N = 9. 9
N must be a whole number:
9 FFs can count from 0 to 29-1, or 0 to 51110
10 FFs can count from 0 to 210-1, or 0 to 102310
Therefore Answer is 10 FFs
23
Assuming the counter is holding 0101. What

will be the count after 27 clock pulses?
D
CLK
CLK
CLK
J
CLK
24
Assuming the counter is holding 0101. What will be

the count after 27 clock pulses?
D
CLK
CLK
CLK
J
CLK
01012 = 510
5 + 27 = 32
MOD 16 counter counts from 0 to 15, 0 to 15,
(keep subtracting 16 until the number is less than 16)
32 16 = 16
16 16 = 0
Ans: 0000
25
In an asynchoronous counter, all FFs change

states at the same time.
True or False?
26
In an asynchoronous counter, all FFs

change states at the same time.
True or False?
Ans: False
27
Looking at the frequency division application

of the counter e.g.
LSB
MSB
D
CLK
CLK
CLK
J
CLK
Remember, the mod number of this counter is 24 = 16
28
Frequency Division - revision

e.g.
CLK
16 khz
A
8 khz
B
4 khz
C
2 khz
D
1 khz = fCLK / Mod Number = 16 / 16

29
Frequency Division MSB Frequency

In general, for any counter,
fCLK
fMSB = -------------------Mod Number
Mod N counter is also called divide-by-N
counter.
30
7.2 Counters with MOD number < 2N
2 FFs - can build MOD 4 (22) counter

3 FFs can build MOD 8 (23) counter
...
How do we build a counter with MOD number < 2N ?
31
e.g. lets build a Mod 6 counter

A basic mod 6 counter counts from 0 to 5 and repeats
If we use 2 FF, it can only count from 0 to 3
If we use 3 FF, it can count from 0 to 7.

therefore, we need 3 FFs,
32
e.g. lets build a Mod 6 counter

C
CLK
CLR
CLK
CLR
J
CLK
CLR
without modification this makes a MOD-8 counter
i.e. it will count from 0 to 7 and repeat
33
Building a MOD 6 Counter

C
CLK
CLR
CLK
CLR
J
CLK
CLR
Well modify this to make it a MOD-6 counter

i.e. counting from 0 to 5 and repeats
but, how do we make it count from 0 to 5 only?
We can reset the counter to 0 every time the counter count up to 6
34

C
CLK
CLR
CLK
CLR
J
CLK
CLR
and, we can make use of CLR to reset the counter to 0

Remember, CLR is an asynchronous control input, when it is active,
Q is forced to 0 immediately.
35

C
CLK
CLR
CLK
CLR
J
CLK
CLR
How do we know when the counter reaches 6 ?

We will decode the counter outputs !!!
36

1
CLK
CLR
CLK
CLR
J
CLK
CLR
610 = 1102
when the counter reaches 6 C=1, B=1, A=0
And we want to clear the counter when the counter reaches 6
37

1
CLK
CLR
CLK
CLR
J
CLK
CLR
The CLR input is active LOW, we need to produce a 0

when the counter reaches 6, in order to reset the counter.
i.e. we need to build a circuit that will produce a 0 when
C=B=1.
How
?
38

1
CLK
CLR
CLK
CLR
J
CLK
CLR
Why is it that we only need to consider C=B=1, how about A?

This is because, the counter will count from 0 to 6,
i.e. 000001010011100101110
Notice that the moment C=B=1, the counter has reached 6 !
39

1
CLK
CLR
CLK
CLR
J
CLK
CLR
All CLR inputs are connected

to the decoding circuit output
C
B
Decoding Circuit
detecting 6 to produce 0
40
MOD 6 Counter in action

0
0
C
0
B
CLK
CLR
0 C
0 B
0 10
A
CLK
CLR
J
CLK
CLR
does not reset counter
41

0
0
C
1
B
CLK
CLR
0 C
0 B
1 10
A
CLK
CLR
J
CLK
CLR
42

0
1
C
0
B
CLK
CLR
0 C
1 B
2 10
A
CLK
CLR
J
CLK
CLR
43

0
1
C
1
B
CLK
CLR
0 C
1 B
310
A
CLK
CLR
J
CLK
CLR
44

1
0
C
0
B
CLK
CLR
1 C
0 B
4 10
A
CLK
CLR
J
CLK
CLR
45

1
0
C
1
B
CLK
CLR
1 C
0 B
5 10
A
CLK
CLR
J
CLK
CLR
46

1
1
C
0
B
CLK
CLR
1 C
1 B
6 10
A
CLK
CLR
J
CLK
CLR
reset counter
Note, the moment the counter reaches 6,
it resets to 0. i.e. it is momentary
47

0
0
C
0
B
CLK
CLR
0 C
0 B
0 10
A
CLK
CLR
J
CLK
the cycle repeats
CLR
48
State Transition Diagram

000
110
101
CBA
Note: The
moment the
counter reaches
110, it resets
immediately to 0.
Therefore the
count sequence is
from 0 to 5
001
010
011
100
49
MOD-6 Counter Waveform

1
10
11 12
CLK
Note: Some
waveforms
are no more
symmetrical
C
Decoder
output
001
000
010
011
101 000
011
101 000 001
100
100
110
010
110
50
Draw a state diagram for MOD-7 counter.
51
Draw a state diagram for MOD-7 counter.

000 CBA
001
110
010
101
100
011
52
What is the MOD number of the counter?

D
CLK
CLR
CLK
CLR
CLK
CLR
30kHz
CLK
CLR
B
C
D
53
What is the MOD number of the counter?

Hence a MOD 14 counter. Count from 0 to 1310.
D
CLK
D
CLR
CLK
CLR
B
C
D
CLK
CLR
30kHz
CLK
CLR
reset at D=1 C=1 and B=1

i.e. reset at 1110 (=1410)
54
What is the frequency at output D?
CLK
CLR
CLK
CLR
CLK
CLR
30kHz
CLK
CLR
B
C
D
55
What is the frequency at output D?

CLK frequency / MOD Number = 30kHz/14 = 2.14kHz
D
CLK
CLR
CLK
CLR
CLK
CLR
30kHz
CLK
CLR
B
C
D
56
General Design Procedure

To construct a MOD X counter
Find the smallest number of FFs required,

such that 2N >= X. If 2N = X stop.
or else
Connect a NAND output to the asynchronous

CLR inputs of all FFs.
Determine which FF outputs will be HIGH

at the count = X then connect them to the
NAND inputs.
57
Construct a MOD-10 counter.
58
How many FFs required? Reset at 1010

D
CLK
CLR
CLK
CLR
D
B
CLK
CLR
CLK
CLR
This is also known as

a DECADE counter
59
Decade Counters / BCD Counters

A decade counter is any counter that has 10
distinct states, no matter what the sequence.
e.g. 0-1-2-3-4-8-9-10-11-12
A decade counter which counts in sequence
from 0000 to 1001 is known as BCD counter
60
Application of Counter: Digital Clock

60Hz
60Hz
Pulse
shaper
1Hz
MOD-60
counter
Counters
displays, etc
http://www.howstuffworks.com/digital-clock1.htm
61
62
FFs is required
Counter should reset when it reaches
Q5, Q4, Q3, Q2
111100
should be connected be to
to the NAND inputs
63

Next, we are going to learn the counter IC which we will be using in the Lab
IC Asynchronous Counters 74LS293
64
7.3 IC Asynchronous Counters

J
CP0
CP
CD
CP
CD
CP
CD
Q
CP
CD
CP1
MR2
MR1
Q0
Q1
Q2
Q3
65

Take note
There are 2 clock inputs, CP0 is for the 1 st FF, CP1 is for the 2nd FF
1st FF output (Q0) is not connected to the CLK of 2 nd FF
2nd, 3rd and 4th FFs are already cascaded internally (forming a group
of 3 FFs)
If you need all 4 FFs, remember to connect Q0 to CP1, and feed
the clock to CP0.
If no decoding is required (i.e. no need to reset counter), connect
MR1, MR2 to 0,
66

We will use this symbol in our counter design
CP0
74LS293
CP1
MR2
MR1
Q0
Q1
Q2
Q3
67
Construct a MOD-2 counter using 74LS293.
68

Require 1 FF, CLK connect to CP0
No special reset required because 21 = 2 exactly
CP1
CP0
74LS293
MR1 MR2
Q3 Q2 Q1 Q0 Obtain output
X X X from Q0
69
Construct a MOD-8 counter using

74LS293.
70

Require 3 FFs, CLK connect to CP1
CP1
CP0
74LS293
MR1 MR2
Q3 Q2 Q1 Q0 Obtain output
from Q3 Q2 Q1
MSB LSB X
71
72

Require All 4 FFs, Q0 must connect to CP1
CLK connect to CP0
CP1
CP0
74LS293
MR1 MR2
Q 3 Q2 Q 1 Q 0
MSB
Obtain output
from Q3 Q2 Q1 Q0
LSB
73
Construct a MOD-10 counter using 74LS293
74
Require 4 FFs, Q0 must connect to
CP1
Count from 0000 to 1001, reset at 1010

Q3 Q1
CP1
CP0
74LS293
MR1 MR2
Q 3 Q2 Q 1 Q0
MSB
LSB
75
76

Require 4 FFs, Q0 must connect to CP
Count from 0000 to 1101, reset at 1110
1
CP1
CP0
Q3Q2Q1
74LS293
MR1 MR2
Q 3 Q2 Q 1 Q 0
Q0: LSB
Q3: MSB
77
FFs is required.
2 74LS293 are required
Counter should reset when it reaches
111100
We can use the group of 3 FFs from each IC
78
CP1
CP0
CP1
74LS293
CP0
MR1 MR2 Q3Q2 Q1Q0

QCQBQA
74LS293
MR1 MR2
Q 3 Q 2 Q 1Q 0
QF QE QD
79
MOD-? Counter
CP1
CP0
CP1
74LS293
CP0
MR1 MR2 Q3Q2Q1Q0
74LS293
MR1 MR2
Q 3 Q 2 Q 1Q 0
MOD-6
MOD-10
80
MOD-? Counter
CP1
CP0
CP1
74LS293
fin
CP0
74LS293
MR1 MR2
MR1 MR2 Q3Q2Q1Q0
fin/10
MOD-10
Q 3 Q 2 Q 1Q 0
MOD-6
fin/10/6
= fin/60
81
MOD-? Counter
CP1
CP0
CP1
74LS293
fin
CP0
MR1 MR2 Q3Q2Q1Q0
74LS293
MR1 MR2
Q 3 Q 2 Q 1Q 0
fin/60
MOD-10
MOD-6
Overall MOD Number = 10 x 6 = 60

82
Counting in Binary Sequence

vs Non- Binary sequence
Notice that in the last 2 examples:
Both are MOD 60 counter, they are built differently!!!

Do they count differently? YES
The 1st one count in binary sequence, the 2nd one does not.
However the MSB waveform of both counters are not
symmetrical (not a square wave).
To obtain symmetrical waveform, the mod 60 must be built
as a cascade such as Mod-15 followed by mod 4, whereby
the MSD unit is a Mod 2N counter.
83
Summary
For mod number = 2N, tie MR1 and MR to ground
For mod number <= 8, use the 3-bit ripple counter
section (Q3 Q2 Q1) with clock at CP1
For mod number > 8 but <=16, connect Q0 to CP1 and
CP0
clock input to
For mod number >16, cascade additional ICs
Two or more counters can be cascaded to provide an
overall MOD number equal to the product of their
individual MOD numbers
84
Using 74293ICs design

a) a MOD-6 counter that counts in a binary sequence
b) a MOD-6 counter with a square wave output
To have the MSB waveform symmetrical

(a square wave), if MOD number is not =
2N, then cascade 2 counters, make sure
the 2nd MOD number is = 2N.
85
(a) This is a MOD-6 counter that counts in a binary sequence

CP1
CP0
74LS293
MR1 MR2 Q3Q2Q1Q0
Draw the Q3
waveform, and
examine the
counting sequence
86
MOD-6 Counter Waveform (a)

1
10
11 12
CLK
Q1
Q2
Q3
001
000
010
011
100
101
000
011
001
010
100
Note: MSB
(Q3)
waveform is
not
101 000 symmetrical
But the count is in Binary Sequence

87
(a) This is a MOD-6 counter with a square wave output

CP1
CP0
74LS293
CP1
CP0
74LS293
MR1 MR2 Q3Q2Q1Q0

C
MR1 MR2 Q3Q2Q1Q0

B A
MOD 2
MOD 3
Overall MOD Number = 3 X 2 = 6
Draw the C waveform,

and examine the
counting sequence
88
MOD-6 Counter Waveform (b)

1
10
11 12
CLK
Note: MSB
(C)
waveform is
symmetrical
001
000
010
100
101
110
000
100
001
010
110
101
000
But the count is not in Binary Sequence

89
Using 74293ICs design

a) a MOD-24 counter that counts in a binary sequence
b) a MOD-24 counter with a square wave output
Draw the MSB waveforms and state transition
Diagram to convince yourself.
90
(a) This is a MOD-24 counter with a square wave output
CP1
CP0
fin
CP1
74LS293
D
MR1 MR2 Q3Q2Q1Q0
24 = 12 * 2 ,
CP0
74LS293
E
MR1 MR2
Q 3 Q 2 Q1 Q0
1210 = 11002
91
(b) This is a MOD-24 counter that counts in a binary sequence
CP1
CP0
74LS293
fin
CP1
CP0
MR1 MR2 Q3Q2Q1Q0
74LS293
E
MR1 MR2
Q 3 Q 2 Q1 Q0
5 F/Fs needed
Reset at 2410 = 110002
92
End of Counters and Registers Part 1
93

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Instructions for using the PowerPoint slides:

To view the animated steps - click anywhere on the slide.

Chp 7 Counters & Registers

7. Counters & Registers Part 1

MSI Logic Circuits

Chp 7 Counters & Registers

Counters & Registers - Part 1

Asynchronous (ripple) Counters

Counters with MOD number < 2N

Asynchronous Down Counter

Propagation Delay in Ripple Counters

Chp 7 Counters & Registers

Chp 7 Counters & Registers

Chp 7 Counters & Registers

JK F/F using it to build a counter

J K F/F -- to use it to build a counter

Chp 7 Counters & Registers

JK F/F using it to build a counter

J K F/F -- to use it to build a counter

Chp 7 Counters & Registers

J K F/F - - how does it work as a counter?

The count goes 0, 1, 0 , 1

The cycle repeats after every 2 states

Mod 2 counter building on - 1

How do we make it count more than 1?

All J, K, preset, clear = 1

Cont on Next slide

Chp 7 Counters & Registers

Mod 2 counter building on - 2

Where the clock is fed

All J and K inputs = 1

Chp 7 Counters & Registers

Mod 2 counter building on - 2

All J and K inputs = 1

Chp 7 Counters & Registers

7.1 Asynchronous Counters

All J, K, preset, clear = 1

Chp 7 Counters & Registers

7.1 Asynchronous Counters

Where is the LSB and where is the MSB?

Chp 7 Counters & Registers

7.1 Asynchronous counters

Obtain the Counter - waveform

Chp 7 Counters & Registers

7.1 Asynchronous Counters

In the previous e.g.

Chp 7 Counters & Registers

7.1 Asynchronous Counters

The counters in our examples are ALL

Chp 7 Counters & Registers

7.1 Asynchronous Counters

Asynchoronous (ripple) counters

Chp 7 Counters & Registers

7.1 Asynchronous counters

Defining MOD number ?

Chp 7 Counters & Registers

7.1 Asynchronous counters

Mod Number & Number of Flip Flops

Chp 7 Counters & Registers

7.1 Asynchronous counters

What would the MOD number of the

Chp 7 Counters & Registers

7.1 Asynchronous counters