ARM7- LPC 2148

processor
Saravana selvan.D

What is ARM?
ARM-Advanced RISC Machine is a 32-bit RISC (Reduced Instruction
Set Computer) processor architecture developed by ARM Holdings.
Sometimes misunderstood that the ARM is microcontroller or processor but in
reality, ARM is anarchitecture which is used in many processors and
microcontrollers.
The ARM architecture licensed to companies that want to manufacture ARMbased CPUs or System-on-Chip products.
This enables the companies to develop their own processors compliant with
the ARM instruction set architecture.
For example, the device we are using LPC2148 is ARM architecture based SOC
product developed by NXP Semiconductor. Similarly, all major semiconductor
manufacturers like Atmel, Samsung, TI etc. they all make ARM based SOCs.

RISC/CISC
what is CISC ?
A complex instruction set computer (CISC
/pronounce as sisk/) is a computer where single
instructions can execute several low-level
operations (such as a load from memory, an
arithmetic operation, and a memory store) or are
capable of multi-step operations or addressing
modes within single instructions, as its name
suggest COMPLEX INSTRUCTION SET.
What is RISC ?
A reduced instruction set computer (RISC
/pronounce as risk/) is a computer which only
use simple instructions that can be divide into
multiple instructions which perform low-level
operation within single clock cycle, as its name
suggest REDUCED INSTRUCTION SET

Examples of CISC instruction set architectures are PDP-11, VAX, Motorola 68k,
and your desktop PCs on intels x86 architecture based too .
Examples of RISC families include DEC Alpha, AMD 29k, ARC,
Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power
(including PowerPC), SuperH, SPARC and ARM too.

About ARM
ARM architecture has become the most popular 32-bit architecture in the world, with
wide range of ICs available from various IC manufacturers.
ARM7 & Cortex series is largest success of ARM . ARM processors are embedded in
products ranging from cell/mobile phones to automotive braking systems.
A worldwide community of ARM partners and third-party vendors has developed among
semiconductor and product design companies, including hardware engineers, system
designers, and software developers. Apple, NXP, ST microelectronics,NVidia,
Qualcomm, Samsung Electronics, and Texas Instruments, etc.
According to ARM Holdings, producers of chips based on ARM architectures reported
shipments of 6.1 billion ARM Based processors, representing 95% of smartphones, 35%
of digital televisions and set-top boxes and 10% of mobile computers. It is the most
widely used 32-bit instruction set architecture in terms of quantity produced.

ARM SERIES OF
ARCHITECTURE

ARM has introduced many processors. Each set or groups of processors are
having different core and different Features. Development of the ARM
Architecture is started with 26 bit processors and nowadays it reach upto 64 bit.
ARM Classic series
The classical ARM series refers to processors starting from ARM7 to ARM11. This is the
series which gives market boost to ARM because of its core features like Data Tightly
Coupled memory, cache, MMU, MPU, etc. Typical examples of this series
areARM7TDMI,ARM926EJ-S,ARM11 MPCore, etc.
Cortex-A series: A-profile, the Application profile
In thisCortex architecture, we port different embedded OS and designembedded system
by OS system programming. The core feature of this profile is Highest performance at low
power, TrustZone and Jazelle-RCT for a safe and extensible system. Practical
development platform of this types of profile is Friendly ARM, Raspberry Pi, etc.
Cortex-R series: R-profile, the Real-time profile:
This is Cortex architecture which mostly used for real time purpose where application
abort is critical situation contain core features likeProtected memory (MPU), Low latency
and predictability real-time needs.
Cortex-M series: M-profile, the Microcontroller profile:
This profile is specially dedicated for microcontroller purpose only. The core feature of this
profile is like Lowest gate count entry point, Deterministic and predictable behavior a key
priority, Deeply embedded use. Typical example of this kind of profile architecture is

ARM Architectures
Revision/Processor Variants

LPC2148-NXP semiconductor
(Philips)
ARM7 is most successful and widely used processor family in embedded system
applications. So we have decided to choose ARM7 TDMI based NXP controller
LPC2148. Also, ARM7 is abalance between classic and new Cortex series.

LPC2148is the widely used IC from ARM-7 family. It is manufactured by Philips (NXP)and it is pre-loaded with many inbuilt
peripherals making it more efficient and a reliable option for the beginners as well as high end application developer.

MEMORY
LPC2148 has 32kB on chip SRAM and 512 kB on chip FLASH memory. It has inbuilt support up to 2kB end point USB RAM also.
This huge amount of memory is well suited for almost all the applications.
We will explain the basic functions of above memory.

1.On chip FLASH memory system

The LPC2148 incorporates a 512 kB Flash memory system. This memory may be used for both code and data storage. The
FLASH memory can be programmed by means of
1. Serialbuilt-in JTAG interface
2. Using In System Programming (ISP) and UART0or
3. By means of InApplication Programming (IAP) capabilities.
The application program, using the IAP functions, may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When the LPC2148 on-chip boot loader is
used, 500 kB of Flash memory is available for user code.
The LPC2148 Flash memory provides minimum of 100,000 erase/write cycles and 20 years of data-retention.
2.On chip SRAM
The LPC2148 provides 32 kB of static RAM which may be used for code and/or data storage. It may be accessed as 8-bits, 16bits, and 32-bits.

I/O Ports
LPC 2148 has two I/O Ports each of 32 bit wide giving us total 64 I/O Pins. Ports are named as P0 and P1.
Pins of each port are labelled as PX.Y where X stands for port number, 0 or 1 where else Y stands for pin number 0 to 31.
Each pin can perform alternate functions also. For eg. P0.8 serves as GPIO as well as transmitter pin of UART1, PWM4 and
AD1.1.
On RESET, each pin is configured as GPIO. For any of the other use, programmer mustconfigure it properly.

Block diagram of ARM7

Instruction Decoder and Logic Control: The
Architecture
function of instruction decoder and logic control is
to
decode instructions and generate control signals to
other parts of processor for execution of
instructions.
Address Register: To hold a 32-bit address for
address bus.
Address Increment: It is used to increment an
address by four and place it in address register.
Register Bank: Register bank contains thirty one
32-bit registers and six status registers.
Barrel Shifter: it is used for fast shift operation
ALU: 32-bit ALU is used for Arithmetic and Logic
Operation.
Write Data Register: The processor put the data
in Write Data Register for write operation.
Read Data Register: When processor reads from
memory it places the result in this register.

Modes of operation
1.User
mode

all
normal
application run under this mode
2.FIQ mode all fast interrupt data
transfer
or
channel
process
service provided under this mode
3.IRQ mode vectored(priority
based) interrupt handler
4.Supervision mode protected
mode for the operating system
5.System mode all operating
related task
6.Abort mode entered after a
data or instruction Pre-fetch Abort
exception
7.Undefined mode entered when
an
undefined
instruction
is
executed.

ARM Register sets

CPSR Current program

status register
SPSR Saved program
status register
LR Link register
SP Stack Pointer
PC Program Counter

General purpose registers hold

either data or an address. The
active registers available in
user mode are
r0-r15 and cpsr. spsr is also
available in other than user
mode.
r0-r12 are 32 bit general
purpose registers.
r13-r15 are special purpose 32
bit registers.
r13 stack pointer which holds
top of stack address
r14 Link register where the
core puts return address during
call.
r15 program counter contains
the address of next instruction
to be fetched.
cpsr Current program status
register which is used by the
ARM core for monitoring and
control
internal operations. The fields

Current/State Program Status

Register (CPSR / SPSR)

Condition code flags (Bit 28 to 31)

V = ALU operation oVerflowed
C = ALU operation Carried out
Z = Zero result from ALU
N = Negative result from ALU
Sticky Overflow flag Q flag (Bit 27)
Architecture 5TE and later only
Indicates if saturation has occurred
J bit(Bit 24)
Architecture 5TEJ and later only
J = 1: Processor in Jazelle state
Interrupt Disable bits(Bit 6 Bit 7)
I = 1: Disables IRQF = 1: Disables FIQ

T Bit (Bit 5)
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Introduced in Architecture 4T
Mode bits (Bit 0 to 4)
Specify the processor mode
New bits in V6 (Bit 10 to 19)
GE[3:0] used by some SIMD instructions
E bit controls load/store endianness
A bit disables imprecise data aborts
IT [abcde] IF THEN conditional
execution of Thumb-2 instruction groups

GPIO in LPC 2148

PORT 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 28 pins
of the Port 0 can be used as a general purpose bi-directional digital I/Os while P0.31
provides digital output functions only. The operation of port 0 pins depends upon the pin
function selected via the pin connect block. Pins P0.24, P0.26 and P0.27 are not
available.
PORT 1 is a 32-bit bi-directional I/O port with individual direction controls for each bit.
The operation of port 1 pins depends upon the pin function selected via the pin connect
block. Pins 0 through 15 of port 1 are not available.
PORT PINS
P0.0-P0.31
P1.16-P1.31

TYPE

DESCRIPTION

Input/output

General purpose
input/output. The number
of GPIOs actually
available depends on the
use of alternate functions.

PORT0 and PORT1 are controlled via two

groups of registers
IOPIN
This is GPIO Port Pin value register. The Current State of the GPIO configured port
pins can always be read from this register, regardless of pin direction.
IODIR
This is GPIO Port Direction control register. This register individuallyControls the
direction of each Port Pin.
IOCLR
This is GPIO Port Output Clear registers. This register controls the state of output
pins. Writing ones produces lows at the corresponding port pins and clears the
corresponding bits in the IOSET register. Writing zeroes has no effect.
IOSET
This is GPIO Port Output Set registers. This register controls the state of output
pins in conjunction with the IOCLR register. Writing ones produces highs at the
corresponding port pins. Writing zeroes has no effect.
These are the set of register used to configure I/O Pins.

IOSEL0
Port 0 has 32 pins (P0.0 to P0.31). Each pin can have multiple functions. On RESET, all pins are configured as GPIO pins.
However we can re-configure using the registers IOSEL0 and IOSEL1.

00

Function 0 (Default Function=

GPIO)

01

Function 1

10

Function 2

IOSEL011
is used to select function of P0.0 to P0.15. EachFunction
pin has up to34 functions so 2 bits/pin in IOSEL0 is provided for selecting
function.
IOSEL1
IOSEL1 is used to select function of Pins P0.16 to P0.31
IOSEL2
IOSEL2 is used to select function of Pins P1.16 to P1.31
IO0DIR
IO0DIR is used to configure pins of Port 0-P0 as input or output pins.
1= Output Pin
0= Input Pin
Example: IO0DIR=0x0000FFFF means P0.0 to P0.15 are configured as output pins and P0.16 to P0.31 are configured as input
pins.

IO1DIR
IO1DIR is used to configure pins of Port 1-P1 as input or output pins.
1= Output Pin
0= Input Pin
Example: IO1DIR=0xAAAAAAAA means even pins (P1.0, P1.2, P1.4 etc.) are configured as
input pins and odd pins (P1.1, P1.3, P1.5 etc.) are configured as input pins.
IO0SET
It is used to set pins of Port0-P0 to logic 1.
Example: IO0SET=0x0000FFFF will set pins P0.0 to P0.15 at logic 1. It will not affect other pins.
IO0CLR
It is used to set pins of Port0-P0 to logic 0.
Example: IO0CLR=0x0000FFFF will set pins P0.0 to P0.15 at logic 0. It will not affect other
pins.
IO1SET
It is used to set pins of Port1-P1 to logic 1.
Example: IO1SET=0xFFFF0000 will set pins P1.16 to P1.31 at logic 1. It will not affect other
pins.
IO1CLR
It is used to set pins of Port1-P1 to logic 0.
Example: IO1CLR=0xFFFF0000 will set pins P1.16 to P1.31 at logic 0. It will not affect other
pins.

LED BLINK

unsigned int delay;

int main(void)
{
IO0DIR = (1<<10); // Configure P0.10
as Output
while(1)
{
IO0CLR = (1<<10); // CLEAR (0) P0.10 to
turn LED ON
for(delay=0; delay<500000; delay++); //
delay
IO0SET = (1<<10); // SET (1) P0.10 to
turn LEDs OFF
for(delay=0; delay<500000; delay++); //
delay
}
}

LED BLINK
Blink LEDs connected on pins P0.10-P0.13
//Program for the same below
#include
#include
int main(void)
unsigned int delay;
{
int main(void)
unsigned int delay;
{
PINSEL0=0x00000000; //Port0 set to GPIO
IO0DIR = (0X80000000); // Configure P0.31 as IO0DIR=0x00003C00; //
Output
while(1)
while(1)
{
{
IO0CLR = (1<<31); // CLEAR (0) P0.10 to turn LED
IO0SET=0x00003C00;
ON
for(delay=0; delay<500000; delay++); // delay
for(delay=0; delay<500000; delay++); // delayIO0CLR=0x00003C00;
IO0SET = (1<<31); // SET (1) P0.10 to turn LEDs
for(delay=0; delay<500000; delay++); // delay
OFF
}
for(delay=0; delay<500000; delay++); // delay}
}
}

Add Switch to ARM7 LPC2148

#include <lpc214x.h>
int main(void)
{
IO1DIR &= ~(1<<16); // explicitly making P1.16
as Input
IO0DIR |= (1<<10); // Configuring P0.10 as
Output

while(1)
{
if(!(IO1PIN & (1<<16))) // Evaluates to True for a
'LOW' on P1.16
{
We have to explicitly set the
IO0CLR |= (1<<10); // drive P0.30 LOW, turn LED
direction of port pin in input
ON
mode. Even if by default its in
}else
input mode. Writing 0 at P1.16
{
in the direction control register
IO0SET |= (1<<10); // drive P0.30 HIGH, turn LED
(i.e. IO1DIR) will configure P1.16
OFF
IO1DIR = 0<<16;
instead of IO1DIR
as input.
}
&= ~(1<<16);

}
operator isinstead
because theyof
are fast (code execution) and take care masking. The
and IO0DIR =bitwise
1<<10;
masking
is most important
process which is useful, when we want to perform intended
0.1 or 1.0 =0 (previous values)
return
0;
IO0DIR |= (1<<10)

Neumann architecture and later Harvard architecture was adopted for designing digital
computers.
Von Neumann Architecture:
Von Newmann machines can store program and data in same memory with a
single bus.
An instruction contain the operation command and the address of data to
operated.
Most of the general purpose micro processors such as motorola 6800, intel 8086
use this architecture.
Processor needs two clock cycles to exicute an instruction. The pipelining not
possible with this architectures.
In this first clock cycle the processor gets the instruction from memory and
decodes it. in the next clock cycle the the required data taken from the memory. For each
instruction this cycle repeats. Hence needs two cycles to exicute instruction.
It is simple in hardware implementation but the data and program are required to
share a single bus
Disdvatages:

Limited data paths : this will limit the processing power of processor. The perfamence of
the micro controller depends on word length( no.of bits in data).
The basic von neumann architecture has one serious disdvantage : Everything happens
consequently.
Require to share a single address and data bus.

Harvard
achitecture:

The only diffrence in harvard architecture is that program and

data memories are separated and use phisically separated transmission
paths
Enable the machine to transfer instructions and data
simultaneously.
Processor can exicute an instruction in one cycle if appropriate
pipelinning strategies are implemented.
In this first stage pipelining the instruction to be executed can
be taken from program memory. in this second stage pipelining data is taken
from the data memory using the decode instruction or address.
This architecture is more commanly used in specilized micro
processors for real time and embedded applications.