CMOS

Manufacturing
Process

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 CMOS Process

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Circuit Under Design
VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

This two-inverter circuit (of Figure 3.25 in the text) will be

manufactured in a twin-well process.
Digital Integrated Circuits Manufacturing Process Prentice Hall 1995
 Circuit Layout

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Process Flow

These slides only present only a couple of snapshots of the

manufacturing process for the circuits presented in the textbook.
For a complete overview of all 62 steps, please refer to:
http://tanqueray.eecs.berkeley.edu/~ehab/inv.html.

Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther

and the Simpl program.

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Start Material
A

Starting wafer: n-type with

13 3

A doping level = 10 /cm

* Cross-sections will be

shown along vertical line A-A

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 N-well Construction

(1) Oxidize wafer

(2) Deposit silicon nitride
(3) Deposit photoresist

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 N-well Construction

(4) Expose resist using n-well

mask

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 N-well Construction

(5) Develop resist

(6) Etch nitride and
(7) Grow thick oxide

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 N-well Construction

(8) Implant n-dopants (phosphorus)

(up to 1.5 mm deep)

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 P-well Construction

Repeat previous steps

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Grow Gate Oxide

0.055 mm thin

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Grow Thick Field Oxide

0.9 mm thick

Uses Active Area mask

Is followed by
threshold-adjusting implants

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Polysilicon layer

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Source-Drain Implants

n+ source-drain implant
(using n+ select mask)

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Source-Drain Implants

p+ source-drain implant
(using p+ select mask)

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Contact-Hole Definition

(1) Deposit inter-level

dielectric (SiO2) 0.75 mm

(2) Define contact opening

using contact mask

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Aluminum-1 Layer

Aluminum evaporated
(0.8 mm thick)
followed by other metal
layers and glass

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995

 Advanced Metalization

Digital Integrated Circuits Manufacturing Process Prentice Hall 1995