Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Contents
Objective
Introduction
Motivation
Literature Review
Modified Comparator
Conclusions
References
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Objective

To design a Low-Power, High-Speed

Comparator using Dynamic Offset
Cancellation for high performance
applications
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Introduction
Most system on chip design teams now regard
power as one of their top design concerns.
It is much important that handheld devices
must posses low power.
The Low-Power Design is important for two
factors:
Battery Lifetime (especially for portable
devices)
Reliability
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Motivation
Low Power Design Space
Three ways of performing low power techniques to
reduce power consumption
Voltage
Physical capacitance
Switching activity
Voltage reduction offers an effective means of
power reduction.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Literature Review
Clocked Comparators
Dynamic Offset Cancellation
Conventional Dynamic Comparator [4]
Conventional Double-Tail Comparator [5]
Comparator [6]
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Clocked Comparators
Clocked comparators are often called
Dynamic Comparators. The use of clock can
greatly improve the comparator performance.
Dynamic comparators are widely used in the
design of high-speed ADCs.
Most useful circuits that serve as dynamic
comparators are very fast and are having high
probability of making a decision in a very
short time.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Dynamic Offset Cancellation

Dynamic Comparators accuracy is limited by the
random offset voltage resulting from the device
mismatches.
The input referred offset of the comparator will
degrade the overall performance of the
comparator, so it is better to be minimized.
To calibrate the offset, the differential input of the
comparator are usually tied together to a certain
common-mode voltage and fedback to the state
machine which controls the imbalance.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Conventional Dynamic Comparator [4]

VDD

CLK M5 M7 M8 M6 CLK

Outp
Outn

M3 M4 CL
CL

INN M1 M2 INP

CLK Mtail
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Conventional Dynamic Comparator [4]

Advantages:
High input impedance
Rail-to-Rail output swing
No static power consumption
Disadvantages:
Due to several stacked transistors, a sufficiently
high supply voltage is needed for proper delay
time.
There is only one current path.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Simulation Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Layout Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Conventional Double-Tail Comparator [5]

VDD

CLK Mtail2

M7 M8
Outp
Outn

MR1 M9 M10 MR2

CLK
M3 M4
fp fn

INN M1 M2 INP

CLK Mtail1
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Conventional Double-Tail Comparator [5]

This topology has less stacking and therefore
can operate at lower supply voltages
compared to the conventional dynamic
comparator.
In this comparator, both intermediate stage
transistors will be finally cut-off, hence they
do not play role in improving the effective
transconductance of the latch.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Simulation Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Layout Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Comparator [6]
VDD

CLK Mtail2

M7 M8

Outn Outp

MR1 M9 M10 MR2

VDD

CLK CLK
M3 Mc1 Mc2 M4
fp fn

INN M1 M2 INP

Vfn Msw1 Msw2 Vfp

CLK Mtail1
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Comparator [6]
This comparator is modified for fast
operation even in small supply voltages
compared to the conventional double-tail
comparator.
Without complicating the design and by
adding few transistors, the positive feedback
during the regeneration is strengthened,
which results in remarkably reduced delay
time.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Simulation Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Layout Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Modified Comparator
VDD

M1 M2

M7 M8
Outn
Outp

M5 M3 M4 M6

VDD

Clk
Clk
M9 MC1 MC2 M12

fn fp

Vinn M10 M11 Vinp

Clk M13
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Modified Comparator
The modified comparator requires high accuracy
timing Clkb because the second latch stage has
to detect Vdi in a very short time.
In modified design M1 and M2 are used instead of
Mtail2 and these gates are connected to the Di
nodes.
This improves comparator sensitivity by
increasing the gain of the second latch stage.
Also the clock driving requirements are relaxed
because the modified comparator requires only
a one phase clock.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Simulation Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Layout Results
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Comparison Table
Comparator Conventional Conventional Comparator [6] Modified
Structure Dynamic Double-tail Comparator
comparator [4] Comparator [5]

Technology 180nm 180nm 180nm 180nm

CMOS
Supply voltage 1.2V 1.2V 1.2V 1.2V
(V)
Delay/log(Vin) 285 120 113.5 66.56

(ps/dec)
Power (w) 436.3 337.5 581.3 242.6

Layout Area 16 m x 16 m 28 m x 12 m 38 m x 18 m 33 m x 16 m
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Temperature variations
Comparator -40c 0c 27c 40c
Types
Power Delay Power Delay Power Delay Power Delay
(w) (ps) (w) (ps) (w) (ps) (w) (ps)
Conventional 406.9 265 426.0 275 436.3 285 439.8 293
Dynamic
Comparator
[4]
Conventional 337.5 105 325.1 113 337.5 120 342.1 136
Double -Tail
Comparator
[5]
Comparator 653.2 101 608.3 109 581.3 113.5 569.4 120
[6]
Modified 267.3 56 252.0 61 242.6 66.56 238.3 69
Comparator
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Comparison of power and delay of different

Comparators
700

600

500

400
Power (w)
300 Delay (ps)

200

100

0
Conventional Dynamic Conventional Double-Tail Comparator [6] Modified Comparator
Comparator [4] Comparator [5]
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Comparison of Layout area of different

Comparators
Layout Area (m x m)
800

700

600

500

400

300

200

100

0
Conventional Dynamic Conventional Double-Tail Comparator [6] Modified Comparator
Comparator [4] Comparator [5]
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

Conclusion
This Project has been implemented and
simulated using Cadence Virtuoso tool and
Cadence assura Layout editor. The modified
comparator designed uses low power and
less delay when compared to previously
designed comparators and requires less area
compared to the comparator[6].
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

References
[1] J. Wu, A 100-MHZ pipelined CMOS Comparator, IEEE Journal of Solid
State Circuits, Vol.23, No.6, 1988; pp.1379-1385, doi:10.1109.90034.
[2] B. Goll and H. Zimmermann, Low-power 600MHz comparator for 0.5 V
supply voltage in 0.12 m CMOS, IEEE Electron.Lett., vol. 43, no. 7, pp. 388
390, Mar. 2007.
[3] Y. Jung, S. Lee, J. Chae, and G. C. Temes, Low-power and low-offset
comparator using latch load, Electronics Letters, vol. 47, no. 3, pp. 167-168, Feb.
2011.
[4] M. Miyahara and A. Matsuzawa, A low-offset latched comparator using zero-
static power dynamic offset cancellation technique, in Proc. IEEE Asian Solid State
Circuit Conference, Taipei, Taiwan, Nov.16-18, 2009, pp. 233236.
[5] M. Miyahara,Y. Asada, D. Paik, and A. Matsuzawa, A low-noise self-
calibrating dynamic comparator for high-speed ADCs, in Proc. IEEE Asian Solid
State Circuit Conference (A-SSCC), Fukuoka, Japan, Nov.3-5, 2008, pp. 269272.
[6] Samanch, Babayan-Mashhadi and Reza Loth, Analysis and Design of a Low
Voltage Low-Power Double-Tail Comparator, IEEE Transactions onVLSI Systems,
January, 2013.
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

List of paper based on thesis

V. Deepika and Sangeeta Singh Design and
implementation of a Low-Power, High-speed
Comparator in 2nd International Conference
on Nanomaterials and Technologies (CNT
2014).
Design and Implementation of a Low-Power, High-Speed Comparator using Dynamic Offset Cancellation

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