CONTENT

S.NO NAME OF THE TOPICS NUMBER OF SLIDES

1. CONCEPT OF PIPELINING 3

2. TYPES OF HAZARDS IN PIPELINING 1

3. DATA HAZARD WITH EXAMPLE 3

4. STRUCTURAL HAZARD WITH EXAMPLE 2

5. CONTROL HAZARD 1

6. REFERENCES 1
 WHAT IS PIPELINING??

• A form of computer organization in which successive steps of

an instruction sequence are executed in turn by a sequence of
modules able to operate concurrently , so that another
instruction can be begun before the previous one is finished.

S1 S2 S3 S4

Register Register Register Register Register

Example: Building a car
Unpipeline system Pipeline system

Engine body Paint

24hrs 8hrs Engine body Paint

Engine body Paint

Jobs jobs Engine body Paint

Time Time
(Break the tasks into smaller stages)
 1 2 3 4 5
IF i1 i2 i3

ID i1 i2 i3

EX i1 i2 i3

WB i1 i2

Hazard??
problems with the instruction pipeline in CPU microarchitectures
when the next instruction cannot execute in the following clock
cycle.
 TYPES OF HAZARDS
 Three common types of hazards :
 Data hazards
 Structural hazards
 Control hazards (branching hazards).

1. Data hazard: When an instruction attempt to use a resource

before it is ready.

 There are three situations in which a data hazard can occur:

• read after write (WR), a true dependency

• write after read (RW), an anti-dependency
• write after write (WW), an output dependency
a) Read after write (WR):
i: Add R1 R2 R3 ; ∕ ∕ R1←R2+R3
j: Sub R4 R1 R6 ; ∕ ∕ R4 ← R1-R6

1 2 3 4 5
IF i j

ID ADD SUB

OF R2 R3 R1 R6

EX R2+ R3 R1-R6

WB R1 ←Result
Inconsistency
• SOLUTION: Delay the pipe
• IDEA: Delay the execution of operand fetch till the result gets stored in
the register which is the cause of inconsistency

1 2 3 4 5 6 7 8

IF I J

ID ADD SUB
DELAY
OF R2 R3 R1 R6

EX R2+R3 R1-R6
WB R1← RESULT R4 ← RESULT
 Condition for checking read after write (WR) hazard: If i<j &
Wi ∩Rj ≠ 0
Example:
i= ADD R1,R2,R3 j=SUB R4,R1,R6

Here in this case , Wi={R1} ,Ri={R2,R3}

Wj={R4}, Rj={R1,R6}

As Wi ∩Rj={R1} & i<j (so WR hazard will occur)

b) Write after read (RW):
i: ADD R1 R2 R3 ; ∕ ∕ R1← R2+R3
j: OR R2 R3 R4 ; ∕ ∕ R2 ← R3 OR R4

If jth instruction gets executed before the ith instruction, then the
ith instruction would add into R1 a modified value of R2 & thus
it would produce an incorrect result. This is called RW hazard.

Condition for checking RW hazard: If i<j and Ri ∩Wj ≠ 0.

In this case, Ri={R2,R3} ,Wj={R2}
Ri ∩Wj={R2} ≠ 0
c) write after write (WW): It occurs when a transaction
tries to write an operand out of order.
Example:
i: R2 ← R4+R7 j: R2 ← R1+R3
If instruction j updates the value of R2 before i, the final value
written into register R2 would be that of instruction i but what
was required was of instruction j.Hence a WW hazard is said to
occur.
Condition for checking:if i<j & Wi ∩Wj ≠ 0.
In this case, Wi={R2}
Wj={R2}
Wi ∩Wj={R2} ≠ 0 (hence WW hazard may occur).
2. Structural hazard : Structural hazard occurs due to a resource
conflict in the pipeline.
Example:
i1: Add R1, R2, R3 ; ∕ ∕ R1←R2+R3
i2: Add R4, R5, R6 ; ∕ ∕ R4←R5+R6
i3: Sub R7, R1, R8 ; ∕ ∕ R7 ← R1-R8

1 2 3 4 5 6
IF i1 i2 i3

ID ADD ADD SUB

R2,R3 R5,R6 R1,R8
EX R2+R3 R5+R6 R1-R8

WB R1 ←RESULT R1 ←RESULT
• Here R1 is used for two purposes, fetching the previous value
and storing the result also in clock cycle 4. That will lead to the
incorrect value.
• Solution:Firstly,store the result in R1 in cc4 and delay the pipe
and then fetch the value of R1 for next instruction.

3. CONTROL HAZARD (BRANCH HAZARD): In many

instruction pipeline microarchitectures , the processor will know
the outcome of the branch when it needs to insert a new
instruction into the pipeline.
Example:
i1
i2 if(condition) //if the condition is false then jump to i6.
i3
i4
i5
i6

1 2 3 4 5 6 7 8

IF i1 i2 I3 i4 i6

i3
ID i1 if(cond.) i6

EX i1 false i6

WB i1 i6
 References:

1. T.H. Cormen, C.E.Leiscrson, and R.L. Rivest,”Introduction to

algorithms”.
2. G.Brassard , and P.Bratley, “Fundamentals of algorithms”,
Thank you