Analog-to-Digital Conversion

Linear Technology ,Texas

Instrumentation, National
semiconductor, Analog devices
 Introduction

• Signals in real world: light, sound,temp,pressure

• When you scan a picture with a scanner what the scanner is doing??
• ADC)

• It is taking the analog information provided by the picture (light) and

converting into digital .

• A digital signal is superior to an analog signal because it is more robust to

noise and can easily be recovered, corrected and amplified. For this
reason, the tendency today is to change an analog signal to digital data.
 Introduction
• Analog signals have infinite states available
– mercury thermometer
– needle speedometer

• Digital signals have two states - on (1) or off (0)

– lights (on or off)
– door (open or closed)

• ADC digitize an analog signal by converting data with infinite states to a series of pulses.

• The amplitudes of these pulse can only achieve a finite number of states.

• The digital data produced by an analog to digital converter is only approximately proportional
to the analog input.

• That's because a perfect conversion is impossible due to the fact that digital information
changes in steps, whereas analog is virtually continuous.
 An analog-to-digital converter (abbreviated ADC,
A/D or A to D)
• It is an electronic circuit that converts continuous signals to discrete digital numbers.

• The digital output may be using different coding schemes, such as binary and two's
complement binary.

• However, some non-electronic or only partially electronic devices, such as shaft encoder, can
also be considered as ADCs.

• Consists of
• Amplifier, Filters
• Sample and Hold Circuit, Multiplexer
• ADC
 Types of data
• Analog data (All values on the time and amplitude are allowed).

• Digital data (Only a few amplitude levels are allowed).

 An analog-to-digital converter
• Conceptually, conversion is a three step process:

----Sampling
--- Quantizing - breaking down analog value into a set of finite states.
--- Coding - assigning a digital word or number to each state.
 Conversion process: Sampling

• Digital system works with discrete states

• The signal is only defined at determined times
• The sampling times are proportional to the sampling period (Ts)
Conversion process: Quantification
The signal can only take determined values
Belonging to a range of conversion (ΔVr)
• Based on number of bit combinations that
the converter can output
• Number of possible states:
N=2n where n is number of bits
• Resolution: Q= ΔVr/N
xs(t)
xq(t)
Q
ΔVr

t
Ts
 Step 2: Quantizing
Output Discrete Voltage
Example: States Ranges (V)
You have 0-10V 0 0.00-1.25
signals. Separate them 1 1.25-2.50
into a set of discrete
2 2.50-3.75
states with 1.25V
increments. 3 3.75-5.00
4 5.00-6.25
5 6.25-7.50
6 7.50-8.75
7 8.75-10.0
 Conversion process: Coding

• Assigning a unique digital word to each

sample
• Matching the digital word to the input signal

xq(t)
N-1
N-2

Q
ΔVr
2
1
0

t
Ts
Coding
 Encoding
Output Output Binary Equivalent
• Here we assign the States
digital value (binary 0 000
number) to each
1 001
state for the
computer to read. 2 010
3 011
4 100
5 101
6 110
7 111
 Accuracy of A/D Conversion
There are two ways to best improve accuracy of
A/D conversion:

• increasing the resolution which improves the

accuracy in measuring the amplitude of the
analog signal.

• increasing the sampling rate which increases the

maximum frequency that can be measured.
Accuracy - Resolution
Accuracy - Sampling Rate
Accuracy
 Accuracy
xq(t)

t
Ts

Higher Sampling rate Higher Resolution

xq(t) xq(t)

t t
Ts
 Analog-to-Digital Converter (How it work)

 Before we sample, we have to filter the signal to limit the maximum frequency of the
signal as it affects the sampling rate.
 Filtering should ensure that we do not distort the signal, ie remove high frequency
components that affect the signal Sampling.
 What the ADC circuit does is to take samples from the analog signal from time to time.
Each sample will be converted into a number, based on its voltage level (as in the figure).
An analog-to-digital converter
 Sampling rate
Nyquist-Shannon theorem: Minimum sampling rate
should be at least twice the highest data frequency of the
analog signal

fs>2*fmax
Sampling Rate - Aliasing
 Terminologies
• Converter Resolution
– The smallest change required in the analog input of an ADC to
change its output code by one level
• Converter Accuracy
– The difference between the actual input voltage and the full-
scale weighted equivalent of the binary output code
– Maximum sum of all converter errors including quantization error
• Conversion Time
– Required time (tc) before the converter can provide valid output
data
• Converter Throughput Rate
– The number of times the input signal can be sampled
maintaining full accuracy
– Inverse of the total time required for one successful conversion
– Inverse of Conversion time if No S/H(Sample and Hold) circuit is
used
 Types of ADCs
• Flash ADC
• Sigma-delta ADC
• Integrating or Dual slope converter
• Successive approximation converter
• Pipelined ADCs (Subranging)
• Other
• Voltage-to-frequency, staircase ramp or single
slope, charge balancing or redistribution,
switched capacitor, tracking, and synchro or
resolver
 Types of ADCs
• ADCs come in several basic architectures, although many variations exist for each
type.
• Different types of test equipment need different types of ADCs.
• For example, a digital oscilloscope needs high digitizing speeds but can sacrifice
resolution. (flash adc)
• PC-plug-in digitizers and RF test equipment use ADCs, which provide better
resolution than flash converters, but at the expense of speed.(Subranging
ADCs/pipelined)
• General-purpose data-acquisition equipment usually falls between scopes and
DMMs for sample speed and resolution.
• This type of equipment uses successive-approximation register (SAR) or sigma-delta
converters.
• A digital multimeter (DMM) needs fine resolution and can sacrifice high measurement
speeds.(Integrating ADCs)
ADC architectures cover differing ranges of
sample rate and resolution.
Common Test Parameters for ADC's
 DAC

• In an electronic circuit, a combination of high voltage (+5V) and low voltage

(0V) is usually used to represent a binary number. For example, a binary
number 1010 is represented by

Weighting 23 22 21 20

Binary Digit 1 0 1 0

State +5V 0V +5V 0V

• DACs are electronic circuits that convert digital, (usually binary) signals (for
example, 1000100) to analog electrical quantities (usually voltage) directly
related to the digitally encoded input number.
 DAC
• DACs are used in many other applications, such as voice synthesizers,
automatic test system, and process control actuator. In addition, they allow
computers to communicate with the real (analog) world.

Input Binary
Number
Analog Voltage
Output
Resistive
Register

Summing Amplifier
Voltage Network
Switch
 DAC
• Register: Use to store the digital input (let it remain a constant value) during the
conversion period.
• Voltage: Similar to an ON/OFF switch. It is ‘closed’ when the input is ‘1’. It is
‘opened’ when the input is ‘0’.
• Resistive Summing Network: Summation of the voltages according to different
weighting.
• Amplifier: Amplification of the analog according to a pre-determined output
voltage range. For example, an operation amplifier
• A typical digital-to-analog converter outputs an analog signal, which is usually
voltage or current, that is proportional to the value of the digital code provided to its
inputs.
• Most DAC's have several digital input pins to receive all the bits of its input digital
code in parallel (at the same time).
• Some DAC's, however, are designed to receive the input digital data in serial form
(one bit at a time), so these only have a single digital input pin
 DAC
• The two most popular types of resistive summing networks are:
• Weighted binary resistance type, and
• Ladder resistance (R-2R) type
• A simple DAC may be implemented using an op-amp circuit known as a
summer, so named because its output voltage is the sum of its input
voltages.
• Each of its inputs uses a resistor of different binary weight, such that if
R0=R, then R1=R/2, R2=R/4, R3=R/8,.., RN-1=R/(2N-1).
• The output of a summer circuit with N bits is:
• Vo = -VR (Rf / R) (SN-12N-1 + SN-22N-2+...+S020)
• where VR is the voltage to which the bit is connected when the digital input
is '1'. A digital input is '0' if the bit is connected to 0V (ground).
• A 4-bit summer circuit is shown in Figure

An Op Amp Summer Circuit Used as a DAC; where

R0 = 2 R1 = 4 R2 = 8 R3
• One problem with this circuit is the wide range of resistor values needed to build a
DAC with a high number of digital inputs.
• Putting thin-film resistors that come in a wide range of values (e.g., from a few kΩs
to several MΩs) on a single semiconductor chip can be very difficult, especially if high
accuracy and stability are required.
• A better-designed and more commonly-used circuit for digital-to-analog conversion
is known as the R-2R ladder DAC, a 4-bit version of which is shown in Fig.
• It consists of a network of resistors with only two values, R and 2R.
• The input SN to bit N is '1' if it is connected to a voltage VR and '0' if it is grounded.
• Thevenin's Theorem may be applied to prove that the output Vo of an R-2R ladder
DAC with N bits is:
•
• Vo = VR/2N (SN-12N-1 + SN-22N-2+...+S020).
 A 4-bit R-2R Ladder DAC

• Thus, the output of the R-2R ladder in Figure 2 is Vo = VR/24 (S323+S222+S121+S020)

or Vo = VR (S3 / 2 + S2 / 4 + S1 / 8 + S0 / 16) .

• In effect, contribution of each bit to the analog output is proportional to its binary

weight .
•
•
Common Test Parameters for
DAC's
 Single-ended ADC
Single-ended ADC: Single-ended ADCs each have one
input (not to be confused with input channels) that
connects to the signal that needs to be converted to digital.
The signal is referenced to either GND or some other fixed
voltage reference. Figure 1 shows the typical
representation of a single-ended ADC.
 Differential ADC:
Differential ADC:
In differential ADCs, two inputs -- the inverting input (Vin-) and non-inverting input
(Vin+) -- are available to the ADC.
Unlike single-ended ADCs, the input signal of differential ADCs is not referenced
to a fixed voltage reference.
Figure shows the typical representation of a differential ADC.
To simplify analysis, it is assumed that the input voltage is "center-tapped" with
half of the voltage above ground and half below ground.
In actuality, the input voltage need not be centered about ground and, as
mentioned above, need not actually be ground referenced.
However, attention must be paid to the acceptable input common-mode voltage
range of the ADC.
The primary advantage of differential ADCs is high common-mode noise
immunity compared to single-ended ADCs. This noise immunity is due to: 1)
the same noise being coupled on both the inverting and non-inverting input
signals of the ADC; and 2) this noise is rejected by common-mode rejection
capabilities of the differential ADC.
In differential ADCs, both input signals are physically run in parallel with each
other. Thus the same amount of noise gets coupled into both the signals. Also,
when both signals are running in parallel and run the same distance (same
trace/wire length), they are in the same phase when they reach the ADC. As
noise coupled on both signals has the same amplitude and same phase, it gets
rejected to provide very high noise immunity. This high noise immunity makes
differential ADCs a best fit in the applications where the output signal from a
sensor is very small and/or noise in the system is very high.
WHEN TO USE SINGLE-ENDED OR DIFFERENTIAL INPUTS
Differential inputs provide a more stable reading when EMI or
RFI is present, and therefore, it is recommended to use them
whenever noise is generally a problem. This is especially true
when measuring THERMOCOUPLE, STRAIN GAGE and
BRIDGE TYPE PRESSURE SENSOR inputs, since they
produce very small signals that are very succeptible to noise.

Single-ended inputs are lower in cost, and provide twice the

number of inputs for the same size wiring connector, since they
require only one analog HIGH (+) input per channel and one
LLGND (-) shared by all inputs. Differential inputs require signal
HIGH and LOW inputs for each channel and one common
shared LLGND. Single-ended inputs save connector space,
cost, and are easier to install.
 flash ADC
• Most high-speed oscilloscopes and some RF test instruments use flash ADCs
because of their fast digitizing rate,
• which now reaches 5 Gsamples/s for off-the-shelf devices and 20 Gsamples/s for
proprietary designs.
• The typical flash converter resolves analog voltages to 8 bits, although some flash
converters can resolve 10 bits
• Parallel flash converters use a bank of comparators that compare the input voltage
to a set of reference voltages across a resistor network.
• The voltages start at a value equal to that for one-half the least-significant bit (LSB)
and increase in equal voltage increments equivalent to one LSB for each
comparator.
• As a result, a 3-bit flash ADC requires 23–1, or seven, comparators.
• Each comparator's output represents one LSB.
• An 8-bit flash converter uses 255 (28–1) comparators.
 flash ADC
• Uses the 2N resistors to form a ladder
voltage divider, which divides the
reference voltage into 2N equal intervals.
• Uses the 2N-1 comparators to determine
in which of these 2N voltage intervals the
input voltage Vin lies.
• The Combinational logic then translates
the information provided by the output of
the comparators
• This ADC does not require a clock so
the conversion time is essentially set by
the settling time of the comparators and
the propagation time of the combinational
.
logic
 flash ADC
• PROS
• Very Fast (Fastest)
• Very simple operational theory
• Speed is only limited by gate and comparator propagation delay
• CONS
• Expensive
• Prone to produce glitches in the output
• .
Each additional bit of resolution requires twice the comparators
 Successive Approximation Register ADC
SAR Converters
• Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are
frequently the architecture of choice for medium-to-high-resolution applications
with sample rates under 5 mega samples per second (Msps).
• Resolution for SAR ADCs most commonly ranges from 8 to 16 bits, and they
provide low power consumption as well as a small form factor.
• This combination of features makes these ADCs ideal for a wide variety of
applications, such as portable/battery-powered instruments, pen digitizers,
industrial controls, and data/signal acquisition.
• As the name implies, the SAR ADC basically implements a binary search
algorithm.
• Therefore, while the internal circuitry may be running at several megahertz (MHz),
the ADC sample rate is a fraction of that number due to the successive-
approximation algorithm.
• SAR converters are the most popular ADCs in measurement products.
.
 SAR Converters
• Although there are many variations for implementing a SAR ADC, the basic architecture is
quite simple.
• The analog input voltage (VIN) is held on a track/hold.
• To implement the binary search algorithm, the N-bit register is first set to midscale (that is,
100... .00, where the MSB is set to 1).
• This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided
to the ADC.
• A comparison is then performed to determine if VIN is less than, or greater than, VDAC.
• If VIN is greater than VDAC, the comparator output is a logic high, or 1, and the MSB of the
N-bit register remains at 1.
• Conversely, if VIN is less than VDAC, the comparator output is a logic low and the MSB of the
register is cleared to logic 0.
• The SAR control logic then moves to the next bit down, forces that bit high, and does another
comparison.
• The sequence continues all the way down to the LSB.
• Once this is done, the conversion is complete and the N-bit digital word is available in the
register.
Simplified N-bit SAR ADC architecture.
 SAR operation (4-bit ADC example).
•Figure shows an example of a 4-bit
conversion.
•The y-axis (and the bold line in the figure)
represents the DAC output voltage.
• In the example, the first comparison shows
that VIN < VDAC.
•Thus, bit 3 is set to 0.
•The DAC is then set to 01002 and the second
comparison is performed.
•As VIN > VDAC, bit 2 remains at 1.
• The DAC is then set to 01102, and the third
comparison is performed.
•Bit 1 is set to 0, and the DAC is then set to
01012 for the final comparison.
•Finally, bit 0 remains at 1 because VIN > VDAC.
 Integrator-based design

• There are few ways of designing analog-to-digital converters using an

integrator. We will discuss one of them: the single-slope ADC.

• We can see a single-slope ADC in the figure.

• We can notes that it is very similar to a ramp counter ADC, as it uses a
counter, but instead of using a DAC, it uses a circuit called integrator, which
is basically formed by a capacitor, a resistor and an operational amplifier.

• The MOSFET transistor makes the necessary control circuit.

• The integrator produces a sawtooth waveform on its output, from
zero to the maximum possible analog voltage to be sampled, set by
-Vref.
• The minute the waveform is started, the counter starts counting from
0 to (2^n-1).
• When the voltage found at Vin is equal to the voltage achieved by
the triangle waveform generated by the integrator, the control circuit
captures the last value produced by the counter, which will be the
digital correspondent of the analog sample being converted.
 A delta-encoded ADC
A delta-encoded ADC has an up-down counter that feeds a (DAC). The
input signal and the DAC both go to a comparator.
The comparator controls the counter.
The circuit uses negative feedback from the comparator to adjust the
counter until the DAC's output is close enough to the input signal.
The number is read from the counter.

- Delta converters have very wide ranges, and high resolution , but
the conversion time is dependent on the input signal level.

- Delta converters are often very good choices to read real-world

signals..
 A Sigma-Delta ADC
• - Also known as a Delta-Sigma ADC over samples the desired
signal by a large factor and filters the desired signal band.

• Generally a smaller number of bits than required are converted

using a Flash ADC after the Filter.
• The resulting signal, along with the error generated by the discrete
levels of the Flash, is fed back and subtracted from the input to the
filter.
• This negative feedback has the effect of noise shaping the error due
to the Flash so that it does not appear in the desired signal
frequencies.
• A digital filter follows the ADC which reduces the sampling rate,
 ADC0808/ADC0809
8-Bit μP Compatible A/D Converters with 8-Channel
Multiplexer

• Features
• Easy interface to all microprocessors
• Operates ratiometrically or with 5 VDC or analog span
• adjusted voltage reference
• No zero or full-scale adjust required
• 8-channel multiplexer with address logic
• 0V to 5V input range with single 5V power supply
• Outputs meet TTL voltage level specifications
• Standard hermetic or molded 28-pin DIP package
• 28-pin molded chip carrier package
• successive approximation as the conversion technique.
• The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature
dependence, excellent long-term accuracy and repeatability, and consumes minimal
power.
• applications from process and machine control to consumer and automotive
applications.
Molded Chip Carrier Package
• Supply Voltage (VCC) 6.5V
• Voltage at Any Pin −0.3V to (VCC+0.3V) Except Control Inputs
• Voltage at Control Inputs −0.3V to +15V
• (START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
• Storage Temperature Range −65°C to +150°C
• Package Dissipation at TA=25°C 875 mW
• Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260°C
Basic Successive Approximation ADC
(Feedback Subtraction ADC)
• It performs conversions on command.
• In order to process ac signals, SAR ADCs must have an input sample-and-
hold (SHA) to keep the signal constant during the conversion cycle.
• On the assertion of the CONVERT START command, the sample-and-hold
(SHA) is placed in the hold mode, and the internal DAC is set to midscale.
• The comparator determines whether the SHA output is above or below the
DAC output, and the result (bit 1, the most significant bit of the conversion)
is stored in the successive approximation register (SAR).
• The DAC is then set either to ¼ scale or ¾ scale (depending on the value of
bit 1), and the comparator makes the decision for bit 2 of the conversion.
• The result is stored in the register, and the process continues until all of the
bit values have been determined.
• When all the bits have been set, tested, and reset or not as appropriate, the
contents of the SAR correspond to the value of the analog input, and the
conversion is complete.
•
 Functional Description
• Multiplexer.
• The device contains an 8-channel single-ended analog signal multiplexer.
• A particular input channel is selected by using the address decoder.
• Table 1 shows the input states for the address lines to select any channel.
• The address is latched into the decoder on the low-to-high transition of the
address latch enable signal.
 CONVERTER CHARACTERISTICS

• The Converter
• The heart of this single chip data acquisition system is its 8-bit analog-to-digital
converter.
• The converter is designed to give fast, accurate, and repeatable conversions over a
wide range of temperatures.
• The converter is partitioned into 3 major sections:
• the 256R ladder network, the successive approximation register, and the comparator.
• The converter’s digital outputs are positive true.
• The 256R ladder network approach was chosen over the conventional R/2R ladder
because of its inherent monotonicity, which guarantees no missing digital codes.
• Monotonicity is particularly important in closed loop feedback control systems.
• A non-monotonic relationship can cause oscillations that will be catastrophic for the
system.
• Additionally, the 256R network does not cause load variations on the reference
voltage.
• The first output transition occurs when the analog signal has reached +1⁄2 LSB and
succeeding output transitions occur every 1 LSB later up to full-scale.
• The successive approximation register (SAR) performs 8 iterations to approximate the
input voltage.
• For any SAR type converter, n-iterations are required for an n-bit converter.
• Figure 2 shows a typical example of a 3-bit converter.
• In the ADC0808, ADC0809, the approximation technique is extended
• to 8 bits using the 256R network.
• The A/D converter’s successive approximation register (SAR) is reset on the positive edge
of the start conversion (SC) pulse.
• The conversion is begun on the falling edge of the start conversion pulse.
• A conversion in process will be interrupted by receipt of a new start conversion pulse.
• Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output
to the SC input.
• If used in this mode, an external start conversion pulse should be applied after power up.
• End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start
conversion.
• The most important section of the A/D converter is the comparator.
• It is this section which is responsible for the ultimate accuracy of the entire
converter.
• It is also the comparator drift which has the greatest influence on the
repeatability of the device.
• A chopper-stabilized comparator provides the most effective method of
satisfying all the converter requirements.
• The chopper-stabilized comparator converts the DC input signal into an AC
signal.
• This signal is then fed through a high gain AC amplifier and has the DC
level restored.
• This technique limits the drift component of the amplifier since the drift is a
DC component which is not passed by the AC amplifier.
• This makes the entire A/D converter extremely insensitive to temperature,
long term drift and input offset errors.
Resistor Ladder and Switch Tree
3-Bit A/D Transfer Curve 3-Bit A/D Absolute Accuracy Curve
• At the beginning of the conversion interval, the signal goes high (or low) and
remains in that state until the conversion is completed, at which time it goes
low (or high).
• The trailing edge is generally an indication of valid output data, but the data
sheet should be carefully studied—in some ADCs additional delay is
required before the output data is valid.

• An N bit conversion takes N steps. In an 8 bit converter, the DAC must settle to 8 bit
accuracy before the bit decision is made, whereas in a 16 bit converter, it must settle
to 16 bit accuracy, which takes a lot longer.
• In practice, 8 bit successive approximation ADCs can convert in a few hundred
nanoseconds, while 16 bit ones will generally take several microseconds.
• The conversion process is generally initiated by asserting a CONVERT START signal.
• The CONVST signal is a negative-going pulse whose positive-going edge actually
initiates the conversion.
• The internal sample-and-hold (SHA) amplifier is placed in the hold mode on this edge,
and the various bits are determined using the SAR algorithm.
• The negative-going edge of the pulse causes the CONVST or BUSY line to go high.
When the conversion is complete, the BUSY line goes low, indicating the completion
of the conversion process.
• In most cases the trailing edge of the BUSY line can be used as an indication that the
output data is valid and can be used to strobe the output data into an external register.
• However, because of the many variations in terminology and design, the individual
data sheet should always be consulted when using a specific ADC.
• An important characteristic of a SAR ADC is that at the end of the conversion time, the
data corresponding to the sampling clock edge isavailable with no "pipeline" delay.
• This makes the SAR ADC especially easy to use in "single-shot" and multiplexed
applications.
• overall accuracy and linearity of the SAR ADC is determined primarily by the internal
DAC.
• Until recently, most precision SAR ADCs used laser-trimmed thin-film DACs to
achieve the desired accuracy and linearity.
• The thin-film resistor trimming process adds cost, and the thin-film resistor values
may be affected when subjected to the mechanical stresses of packaging.

• For these reasons, switched capacitor (or charge-redistribution) DACs have become
popular in newer SAR ADCs.
• The advantage of the switched capacitor DAC is that the accuracy and linearity is
primarily determined by high-accuracy photolithography, which in turn controls the
capacitor plate area and the capacitance as well as matching.
• In addition, small capacitors can be placed in parallel with the main capacitors which
can be switched in and out under control of autocalibration routines to achieve high
accuracy and linearity without the need for thin-film laser trimming.
3-Bit Switched Capacitor DAC
• The operation of the capacitor DAC (cap DAC) is similar to an R-2R
resistive DAC.
• When a particular bit capacitor is switched to VREF, the voltage divider
created by the bit capacitor and the total array capacitance (2C) adds a
voltage to node A equal to the weight of that bit.
• When the bit capacitor is switched to ground, the same voltage is
subtracted from node A.
Timing Diagram