DSP C5000

Chapter 2 Architecture Overview

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Objectives

Describe and compare the basic CPU architecture of the C54x and the C55x Discuss pipeline phases List the key features of the C54x and C55x memory map and peripherals Give a detailed presentation of CPU registers

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What Makes a DSP a Special Processor?

C5000

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Common Architectural Features of DSPs

Data crunching:
MAC- multiply/ accumulate Unit Executes one or more MAC in one clock cycle Internal registers for storing operands and results Multiple internal data memories Auxilary adressing registers (8 or more) with a dedicated ALU Multiple buses and dual access to data memory Separate access to program and data memories

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Common Architectural Features of DSPs

Real-time and Multi-tasking:
Hardware and software interrupt handling Zero overhead loops Pipelined instructions Parallel units Specialised peripherals

Complex Algorithms:
Specialised instructions (Viterbi, LMS) Bit reverse adressing (FFT) Circular buffers (FIR filters)

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General DSP System Block Diagram

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What Constitutes a Good DSP?

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DSP Requires Multiply and Accumulate

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Multiply and Accumulate Unit

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Multiple Buses

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Internal Memory for Fast Access

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Instruction Pipeline for Fast Execution

Instruction is broken into smaller tasks that can be executed in parallel

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Sequential Processing of Instructions

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Less Cycles per Instruction Less Power Consumption

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Texas Instruments C5000 Solutions

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Basic Harvard Architecture 1st DSP Generation

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TMS320C54X DSP Generation Block Diagram

Conventional Harvard DSP architecture

Program Bus

Data Bus

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TMS320C54X Key Features

CPU Advanced multibus architecture with: one program bus, three data buses, and four address buses 40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two 40-bit accumulators 17-bit 17-bit parallel multiplier coupled to a 40-bit dedicated adder non-pipelined single-cycle multiply/accumulate (MAC) operation Compare, select, store unit (CSSU) for the Viterbi operator implementation Two address generators, including eight auxiliary registers (ARn) and two auxiliary register arithmetic units (ARu)

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C54X Memory Blocks

Memory
192K words 16-bit addressable memory space in 3 blocks: 1) 64K-words program** 2) 64K-words data, 3) 64K-words I/O

**extended program memory depending on the

C54X version.

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TMS320C55X DSP Block Diagram

3 Data Read Buses 1 Program Bus

2 Data Write Bus

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TMS320C55x Key Features

32 x 16-bit Instruction buffer queue (IBQ) Two 17-bit x17-bit MAC units One 40-bit ALU One 40-bit Barrel Shifter One 16-bit ALU Four 40-bit accumulators Twelve independent buses: Three data read buses
Two data write buses Five data address buses One program read bus One program address bus

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More C55x Features

User-configurable IDLE Domains Variable length instructions and efficient block repeat operations Dual MAC operations in a single cycle Performs high precision arithmetic and logical operations Shift a 40-bit result up to 31 bits to the left,or 32 bits to the right Performs arithmetic in a simpler ALU of 16 bits. Hold results of computations and reduce the required memory traffic (4 Accumulators)

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Comparison Between C54x and C55x

C54x MACs Accumulators Read buses Write buses Program fetch Address buses Program word size Data word size Auxiliary Register ALUs ALU Auxiliary Registers Data Registers Memory 1 2 2 1 1 4 16 bits 16 bits 2 (16-bit each) 1 (40-bit) 8 0 separate data/prog C55x 2 4 3 2 1 6 8/16/24/32/40/48 bits 16 bits 3 (24-bit each) 1 (40-bit)/1 (16-bit) 8 4 Unified space

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Performances Features Comparison Between C54x and C55x

30 to 160 Million Instructions per Second (MIPS) and MACs for the C54x compared to 140 to 800 MIPS for the C55x (5 times better) Core Power consumption improves by 6 from 0.32 mW/ MIPS for the C54x to 0.05 for the C55x. Variable instruction length (8 to 48 bits) for the C55x and 16 bits for the C54x gives a better code density. C55x has twice as many Macs (2 and 1), Accumulators (4 and 2), program fetch words (32 and 16 bits)

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Same family but big differences!

Short overview of the C54x and C55x

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Convolution with the C54x 1 of 2

Amplitude

Data Read Buses MAC A B z = x2 + x4 + x3 + x1

x4

x3 x2 x1 x0

Time

ALU

y0 = anxn
n=0 MAC *AR2+, *AR3+, A

Single-cycle MAC Single-cycle ADD

ADD @x2, B ...

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Convolution with the C54x 2 of 2

Amplitude

Data Read Buses MAC A B z = x2 + x4 + x3 + x1

x4

x3 x2 x1 x0

Time

ALU

y0 = anxn
n=0 MAC *AR2+, *AR3+, A

Single-cycle MAC Single-cycle ADD

ADD @x2, B ...

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With the C55x it can be done faster!

Amplitude

Data

Coeffs a0 a1 a2 a3

2 taps/cycle

Data Read Buses

t MAC

x4 x3 x2 x1 x0
Results

Time

MAC

y0 = a0x0 + a1x1 + a2x2 + a3x3 y1 = a0x1 + a1x2 + a2x3 + a3x4

AC0 A AC1

C55x: MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1 C54x: MAC *AR2+, *AR3+, A

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C54x Architecture
Program A/D Bus (P) PC XPC DP Decode @x2
Addr Gen

Data Read A/D Bus (C) Data Read A/D Bus (D)

MAC AR0-7 A B

ALU

Data Write A/D Bus (E)

MAC *AR2+, *AR3+, A ADD @x2, B ...

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C55x Architecture
Program A/D Bus Data Read Buses (D, B, C) Instr Buffer Queue
A d d r Gen

PC

ARn

CDP

MAC

MAC

Decode

AC0 AC1

Data Write Buses (E, F) IU PU AU DU

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MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1

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C55x Program and Instruction Units

00_0000 PAB[24]

PC RETA Prog Addr Gen Status Registers Program Flow PPU Interrupts PU

Internal

PDB[32]

External
FF_FFFF

IU Instruction Buffer 64 x 8
48

4-byte packet fetched every cycle Variable-length instruction set (8, 16, 24, 32, 40, 48-bit)

Decoder

Now, the A-unit...

PU

AU

DU

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C55x Addressing Unit (AU)

00_0000
First 64KW Pg 0

BAB[24] CAB[24] DAB[24]

ARAU A d d r G e n

X X X

AR0-7 CDP DP
23/16-bit

CB[16] FF_FFFF
Last 64KW Pg 127

ALU/Shft T0 T1 T2 T3
16-bit

DB[16]

Stack Pointers Circular Buffers

23/16-bit

A-Unit handles all data addressing Xreg: 23 bits, reg: 16 bits Where else could the data go?...

AU

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C55x Data Computation Unit (DU)

00_0000

MAC MAC Internal

BB[16] CB[16]

AC0 AC1 AC2 AC3

40-bit

40-bit ALU Shift

External
FF_FFFF

DB[16]

Viterbi Hardware Transition Regs Bit Operations DU

D-Unit executes most mathematical operations Now, what happens to the result?...

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C55x Writes (E and F buses)

00_0000 EAB[24]

AU

Internal

FAB[24]

DU External
FF_FFFF

EB[16] FB[16]

AC0 AC1 AC2 AC3

32-bit write in one cycle

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C54x Block Diagram 17x17 MAC Unit

Program/Data ROM Program/Data ROM 16K Words 16K Words D(15-0) Program/Data Buses Program/Data Buses A(23-0) MAC 17 x 17 MPY 40-Bit Adder RND, SAT Shifter 40-Bit Barrel (-16, 31) ALU 40-Bit ALU
CMPS Operator (VITERBI)

Program/Data SRAM Program/Data SRAM 128K Words 128K Words

JTAG Test/ JTAG Test/ Emulation Emulation Control Control Muxed GP I/O Muxed GP I/O

Saturation and Rounding Hardware Two 40-bit ACCs 40-bit ALU 40-bit Barrel Shifter Temporary Register Exponent Encoder Program and Data Address Generation Units Compare, Select and Store Unit 4 Internal Bus Pairs External Interface

DMA
Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5

EXP Encoder Accumulators 40-Bit ACC A 40-Bit ACC B

Peripheral Bus Peripheral Bus

Timer Timer 8/16-bit Host Port 8/16-bit Host Port Interface (HPI) Interface (HPI)
Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP)

Addressing Unit 8 Auxiliary Registers 2 Addressing Units Power Management Power Management

PLL Clock PLL Clock Generator Generator S/W Waitstate S/W Waitstate Generator Generator

C5416 example

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Focus on C54x Architecture

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C54x Block Diagram 17x17 MAC Unit

Program/Data ROM Program/Data ROM 16K Words 16K Words D(15-0) Program/Data Buses Program/Data Buses A(23-0) MAC 17 x 17 MPY 40-Bit Adder RND, SAT Shifter 40-Bit Barrel (-16, 31) ALU 40-Bit ALU
CMPS Operator (VITERBI)

Program/Data SRAM Program/Data SRAM 128K Words 128K Words

JTAG Test/ JTAG Test/ Emulation Emulation Control Control Muxed GP I/O Muxed GP I/O

Saturation and Rounding Hardware Two 40-bit ACCs 40-bit ALU 40-bit Barrel Shifter Temporary Register Exponent Encoder Program and Data Address Generation Units Compare, Select and Store Unit 4 Internal Bus Pairs External Interface

DMA
Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5

EXP Encoder Accumulators 40-Bit ACC A 40-Bit ACC B

Peripheral Bus Peripheral Bus

Timer Timer 8/16-bit Host Port 8/16-bit Host Port Interface (HPI) Interface (HPI)
Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP)

Addressing Unit 8 Auxiliary Registers 2 Addressing Units Power Management Power Management

PLL Clock PLL Clock Generator Generator S/W Waitstate S/W Waitstate Generator Generator

C5416 example

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C54x Pipeline
Program A/D Bus (P)

Internal Memory

Data Read A/D Bus (D) Data Read A/D Bus (C) Data Write A/D Bus (E)

Extl Mem I/F

A D

External Memory

Internal: Up to 4 accesses / cycle Pipeline Phases P - generate program address F - get opcode D - decode instruction A - generate read address R - read operands X - execute

External: 1 access / cycle up to 8M words program R A D F P X R A D F P X R A D F

P F D A P F D P F P

X R X A R X D A R X

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Full Pipeline

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C54x Memory and Buses

Program A/D Bus (P)

Internal Memory

Data Read A/D Bus (D) Data Read A/D Bus (C) Data Write A/D Bus (E)

Extl Mem I/F

A D

External Memory

Internal: Up to 4 accesses / cycle

External: 1 access / cycle up to 8M words program

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C54 Pipeline Phases

Pipeline Phases P - generate program address F - get opcode D - decode instruction A - generate read address R - read operands X - execute P F D A P F D P F P R A D F P X R A D F P X R A D F

X R X A R X D A R X

Full Pipeline

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C54x Pipeline Bus/Hardware Use

P F D A R X Generate Program address Get opcode Decode instruction Generate Read address Read operands Generate Write address Execute instruction Write result

PA PD DA/CA DD/CD EA ED

PC Program mem Decoder ARs, ARAU Data mem ARs, ARAU MAC, ALU Data mem

When storing results back to memory, the write is broken into two phases: - generating the write address - writing the result Overlaid onto R & X phases

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Pipeline Implications 1 of 3
What if all data and program are external?
P1 F1 P2 D1 F2 P3 A1 D2 F3 P4 R1 A2 D3 --X1 R2 A3 ---

54x
D
X2 R3 ---X3 F4 P5 -D4 F5 P6 A4 D5 F6 R4 A5 D6 X4 R5 A6 X5 R6

External read conflicts with external fetch Can reduce performance by at least 50%

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How would you avoid this situation?

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Pipeline Implications 2 of 3
When either Program or Data is located internally... fetch and read can occur simultaneously
P1 F1 P2 D1 F2 P3 A1 D2 F3 P4 R1 A2 D3 F4 P5

54x D

or

54x P

X1 R2 A3 D4 F5 P6 X2 R3 A4 D5 F6 X3 R4 A5 D6 X4 R5 A6 X5 R6 X6

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What if both program and data are located internally?

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Pipeline Implications 3 of 3
Program ROM Data ROM SARAM DARAM

P Bus D Bus C Bus E Bus

Extl Mem I/F

A D

There are no conflicts as long as you follow these rules: ROM/SARAM - 1 access per block per cycle DARAM - 2 accesses per block per cycle
Size and number of blocks vary based upon device - refer to memory map

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C5409 Memory Maps

0000 PROGRAM PAGE 0 (64K) 0000 DATA

8M x 16 Program Space 16K x 16 Internal ROM 7FFF

DARAM or External memory

OVLY bit 7FFF

MMR, Scratch, DARAM

64K x 16 Data Space 32K x 16 Internal DARAM

External memory C000 Internal or External memory

VECTORS

External memory C000 DROM bit FFFF External memory or Internal ROM

FF80 FFFF OVLY DROM

Maps most of on-chip DARAM into Program space Maps most of on-chip Program ROM into Data space

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C5409 Program Memory Options (Page 0)

0000 All External MP/MC = 1 Internal/External MP/MC = 0 0000 0000 0080 'RAM' Option OVLY = 1

DARAM External memory External memory 7FFF External memory C000 Internal 16K x 16 ROM Vectors C000 External memory or Internal ROM Vectors

FF80 FFFF

Vectors

FF80 FFFF

FF80 FFFF

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C5409 8M x 16 Program Space

The OVLY bit selects between two different program memory maps:
OVLY = 0 00 0000 00 0000 OVLY = 1 32K DARAM Upper 32K Page 0 External Mem

Page 0 64K words

00 FFFF 00 FFFF

. . . Page 127 64K words

. . .

SAME

7F 0000

7F 0000

32K DARAM

7F FFFF

Upper 32K Page 127 7F FFFF External Mem

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C5409 Data Memory

0000 32K x 16 DARAM 0000 DARAM Block a 2000 DARAM Block b 8000 4000 DARAM Block c External memory F000 FFFF External memory or ROM 6000 DARAM Block d 7FFF 1FFF DARAM Block a 0000 MMR 0060 0080 Scratch

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C5409 Peripheral Overview

54x core

C5409
3 Multi-Channel BSPs: Each offers up to 128-channel rcv/xmt 6-channels: facilitates data/program transfers w/o CPU intervention Host Port Interface: 8-bit interface to host processor Boot Loader: Multiple ways to load program to volatile memory One 20-bit timer: Can generate timer-based interrupts General Purpose I/O: External lines dedicated to I/O Phase Locked Loop: software programmable Idle Modes: Power saving modes and features

McBSP DMA HPI Boot Timers GPIO PLL Power Down

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C54x Review
Name

the buses on the C54x

How

large are the accumulators? many adders are on the part? are the Memory Mapped Registers located? is the Reset Vector located?

How

Where

Where

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C54x Review - Answers

Name

the buses on the C54x

PA,PD CA,CD DA,DD EA,ED

How

large are the accumulators? many adders are on the part? are the Memory Mapped Registers located? is the Reset Vector located?

40 bits
How

2, one in the MAC and the other in the ALU

Where

From 0x00 to 0x5F in Data Memory

Where

0xFF80 in Program Memory

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Focus on C55x Architecture

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Functional Diagram of C5510 1 of 2

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Functional Diagram of C5510 2 of 2

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Pipelines of the C55x

There are 2 independent pipelines: Program fetch pipeline (3 clock cycles) Program execution pipeline (7 clock cycles)

Pipeline execution breaks an operation into smaller pieces that can be executed independently. The fetch pipeline is done inside the Instruction Buffer Unit and fills IBQ The execute pipeline fetches instructions from IBQ and executes them

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C55x Fetch Packet Pipeline

PF1 - gen prog address PF2 - memory wait F - fetch 4-byte packet

PF1 PF2 F PF1 PF2 F PF1 PF2 F 4 bytes

IBQ
64x8

Fetch-packet pipeline fetches 4-byte packets from program memory INTO the IBQ every cycle (unless IBQ is full) Fetch packet pipeline operates independently from execute pipeline
Program Bus

E Data Read Buses (B,C,D) A M I PU IU AU DU F D

Data Write Buses (E,F)

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C55x Execute Pipeline

D AD AC2 R X W AC1

D - decode opcode AD - compute address AC1 - gen read address AC2 - memory wait R - read operands X - execute W - write to memory

D AD AC2 R X W AC1 D AD AC2 R X W AC1

IBQ
64x8
1-6 bytes

D AD AC2 R X W AC1 D AD AC2 R X W AC1 D AD AC2 R X W AC1 D AD AC2 R X W AC1

E Data Read Buses (B,C,D) A M I IU AU DU F D

Data Write Buses (E,F)

Execute pipeline fetches instructions FROM the IBQ, then executes them IU performs fetch/decode from IBQ AU generates operand addresses AU/DU execute instructions X: result to register W: result to memory

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Execute Pipeline Phases 1 of 2

D
Read six bytes from the instruction buffer queue. Decode an instruction pair or a single instruction. Dispatch instructions to the appropriate CPU functional units. Read STx_55 bits associated with data address generation: ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC)

AD
Read/modify registers involved in data address generation. Perform operations that use the A-unit ALU. Decrement ARx for the conditional branch instruction Evaluate the condition of the XCC instruction

AC1
Memory read operations, send addresses on the appropriate CPU address buses.

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Execute Pipeline Phases 2 of 2

AC2
Allows one cycle for memories to respond to read requests.

R
Read data from memory, I/O space, and MMR-addressed registers. Read A-unit registers Evaluate the conditions of conditional instructions.

X
Read/modify registers that are not MMR-addressed. Read/modify individual register bits. Set conditions. Evaluate the condition of the RPTCC instruction. W Write data to MMR-addressed registers or to I/O space (peripheral registers). Write data to memory.

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Program
00_0000 01_0000 05_0000

C5510 Unified Memory Map

Data
MMRs

00_0000 00_0060 00_8000 02_8000

00_00C0 DARAM (32KW)

Internal

Program and data share the same map 2 ways to view the map:
Prog Data
23 23 0 1 0

SARAM (128KW)

External
FF_FFFF
A(24) A(24) D(32) D(32)

1. Program - (Bytes) 7F_FFFF - 16M x 8-bit, linear 24-bit addresses - Used by fetch/decode logic 2. Data (Words) - 8M x 16-bit, segmented into 64K pages, 23-bit address - Most code written by a user will access data

C55xx core

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Memory Access

16M bytes of memory are addressable as program space or data space When the CPU uses program space to read program code from memory, it uses 24-bit addresses to reference bytes. When program accesses data space, it uses 23-bit addresses to reference 16-bit words. In both cases, the address buses carry 24-bit values, but during a data-space access, the least significant bit on the address bus is forced to 0.

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Data Memory
Data space is divided into 128 main data pages (0 through 127) of 64K addresses each. An instruction that references a main data page concatenates a 7-bit main data page value with a 16-bit offset. On data page 0, the first 96 addresses (00 0000h00 005Fh) are reserved for the memory-mapped registers (MMRs).

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I/O Memory

I/O space is separate from data/program space and is available only for accessing registers of the peripherals on the DSP. The word addresses in I/O space are 16 bits wide, enabling access to 64K locations The CPU uses the data-read address bus DAB for reads and data-write address bus EAB for writes. When the CPU reads from or writes to I/O space, the 16-bit address is concatenated with leading 0s.
Example, suppose an instruction reads a word at the 16-bit address 0102h. DAB carries the 24-bit value 00 0102h.

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C5510 Peripheral Overview

Host External Memory EHPI DMA EMIF Boot

C5510 55xx CPU

MCBSP GPIO Timers Power Cache

EHPI - 16-bit host access to memory DMA - 6 Channels (rotating priority) EMIF - Access to EPROM, SRAM, SBSRAM, SDRAM BOOT Loader - From external memory, Host, McBSP

3 Multi-Channel Buffered SPs - High speed sync serial comm General Purpose I/O - 8-bit i/o port Timer/Counters - Two 20-bit timer/counters Power-Down Modes Instruction Cache (24K bytes)

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CPU Registers Description

C54x and C55x

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CPU Registers C54x vs C55x

The study of CPU registers gives a very good understanding on the processor architecture. The C54x DSP is code compatible with the C55x, therefore registers have the same functionally in both DSPs. Registers in the C55x are more complex so we will see their role and give equivalents for the C54x. The following table summarizes the differences.

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C55x CPU Registers and C54x Equivalents 1 of 3

Abbreviation AC0AC3 AR0AR7 BRC0, BRC1 BRS1 BRC1 BSA01, BSA23,BSA45, BSA67, BSA CDP CDPH Name Accumulators 0 through 3 Auxiliary registers 0 to 7 Block-repeat counters 0 & 1 Save register Circular buffer start address registers Coefficient data pointer (low part of XCDP) High part of XCDP Size 40 bits 16 bits 16 bits 16 bits 16 bits 16 bits C54x A,B same BK BRC none none

BK03, BK47, BKC Circular buffer size registers

16 bits 7 bits

none none

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C55x CPU Registers and C54x Equivalents 2 of 3

CFCT CSR DBIER0, DBIER1 DP DPH IER0, IER1 IFR0, IFR1 IVPD, IVPH PC PDP8 REA0, REA1 Control-flow context register Computed single-repeat register Debug interrupt enable registers 0 and 1 Data page register (low part of XDP) High part of XDP Interrupt enable registers 0& 1 Interrupt flag registers 0 and 1 Interrupt vector pointers Program counter Peripheral data page register 8 bits 16 bits 16 bits 16 bits 7 bits 16 bits 16 bits 16 bits 24 bits 9 bits none none none DP(9 ) none IMR IFR IPTR(9 ) PC(16) none REA

Block-repeat end address registers 24 bits 0 and 1

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C55x CPU Registers and C54 Equivalents 3 of 3

RETA RPTC RSA0, RSA1 SP SPH SSP ST0_55ST3_55 T0T3 TRN0, TRN1 XAR0XAR7 XCDP XDP XSP XSSP XPC(not C55) Return address register Single-repeat counter 24 bits 16 bits na. na. RSA SP na. na. ST0,ST1, PMST T TRN na. na. na. na. na.
C548, C549, C5402, C5410, C5420

Block-repeat start address registers 0 and 24 bits 1 Data stack pointer High part of XSP and XSSP System stack pointer Status registers 0 through 3 Temporary registers 0 to 3 Transition registers 0 and 1 Extended auxiliary registers 0 through 7 Extended coefficient data pointer Extended data page register Extended data stack pointer Extended system stack pointer Extended program counter 16 bits 7 bits 16 bits 16 bits 16 bits 16 bits 23 bits 23 bits 23 bits 23 bits 23 bits 7 bits

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Accumulators (AC0AC3)

The C55 contains four 40-bit accumulators:

AC0, AC1, AC2, and AC3 (The primary function of these registers is to assist in data computation in the D unit: ALU, MACs and the shifter.

The four accumulators are equivalent:

any instruction that uses an accumulator can be programmed to use any one of the four.

Each accumulator is partitioned into:

a low word (ACxL), a high word (ACxH), and eight guard bits (ACxG).

Each of portion can be accessed individually:

by using addressing modes that access the memory-mapped registers.

In the TMS320C54x-compatible mode (C54CM = 1), accumulators AC0 and AC1 correspond to TMS320C54x accumulators A and B, respectively.

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Transition Registers (TRN0, TRN1)

The two transition registers are used in the compareand-select-extremum instructions:

When performing two 16-bit extremum selections update TRN0 and TRN1 based on the comparison of two accumulators high words and low words. TRN0 is updated based on the comparison of the accumulators high words; TRN1 is updated based on the comparison of the low words. When performing a single 40-bit extremum selection the selected transition register (TRN0 or TRN1) is updated based on the comparison of two accumulators throughout their 40 bits.

TRN0 and TRN1 can hold transition decisions for the path to new metrics in Viterbi algorithm implementations.

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Temporary Registers (T0T3)

Four 16-bit general-purpose temporary registers: T0T3 can be used for:

Hold one of the memory multiplicands for multiply, multiply-and-accumulate, and multiplyand-subtract instructions Hold the shift count used in addition, subtraction, and load instructions performed in the D unit Keep track of more pointer values by swapping the contents of the auxiliary registers (AR0AR7) and the temporary registers (using a swap instruction) Hold the transition metric of a Viterbi butterfly for dual 16-bit operations performed in the D-unit ALU

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Registers Used to Address Data Space and I/O Space

Auxiliary Registers (XAR0XAR7 / AR0AR7)

The CPU includes eight extended auxiliary registers XAR0XAR7 Each high part ( ARnH) is used to specify the 7bit main data page for accesses to data space.

Each low part ( ARn) can be used as:

A 16-bit offset to the 7-bit main data page (to form a 23-bit address) A bit address (in instructions that access individual bits or bit pairs) A general-purpose register or counter

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ARn and XARn Access

ARn Auxiliary register n and XARn Extended auxiliary register n are accessible via dedicated instructions .
ARn is mapped to memory XARn is not mapped to memory.

ARnH high part of extended auxiliary register n is Not individually accessible.

To access ARnH, you must access XARn.

XAR0XAR7 or AR0AR7 are used in the AR indirect addressing mode and the dual AR indirect addressing mode. Basic arithmetical, logical and shift operations can be performed on AR0AR7 in the A-unit arithmetic logic unit (ALU).

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Coefficient Data Pointer (XCDP / CDP)

CDP is a coefficient data pointer, and CDPH an associated extension register, concatenate the two form the extended CDP that is called XCDP CDPH is used to specify the 7-bit main data page for accesses to data space. The low 16 bits part (CDP) can be used as: A 16-bit offset to the 7-bit main data page (to form a 23-bit address) A bit address (in instructions that access individual bits or bit pairs) A general-purpose register or counter

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XCDP and CDP Accesses

XCDP Extended coefficient data pointer is accessible via dedicated instructions only. XCDP is not a register mapped to memory. CDP Coefficient data pointer is accessible via dedicated instructions and as a memorymapped register CDPH High part of extended coefficient data pointer is accessible via dedicated instructions and as a memory-mapped register

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Circular Buffer Start Address Registers (BSA01, BSA23, BSA45, BSA67, BSAC)

The CPU includes five 16-bit circular buffer start address registers Each buffer start address register is associated with a particular pointer A buffer start address is added to the pointer only when the pointer is configured for circular addressing in status register ST2_55.

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Circular Buffer Size Registers (BK03, BK47, BKC)

Three 16-bit circular buffer size registers specify the number of words (up to 65535) in a circular buffer. Each buffer size register is associated with particular pointers In the TMS320C54x-compatible mode (C54CM = 1), BK03 is used for all the auxiliary registers, and BK47 is not used.

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Data Page Register (XDP / DP)

Data page register, DP, and associated extension register DPH can be concatenated to form an extended DP that is called XDP The high part (DPH) is used to specify the 7bit main data page for accesses to data space. The low part specifies a 16-bit offset (local data page) that is concatenated with the main data page to form a 23-bit address. In the DP direct addressing mode, XDP specifies a 23-bit address, and in the k16 absolute addressing mode, DPH is concatenated with a 16-bit immediate value to form a 23-bit address.

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DP/ XDP Accesses

XDP Extended data page register Accessible via dedicated instruction only. XDP is not a register mapped to memory. DP Data page register accessible via dedicated instructions and as a memory-mapped register DPH High part of extended data page Register is accessible via dedicated instructions and as a memory-mapped register

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Peripheral Data Page Register (PDP)

The 9-bit peripheral data page register (PDP) selects a 128-word page within the 64K-word I/O space.

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Stack Pointers (XSP / SP, XSSP / SSP)

The data stack pointer (SP), a system stack pointer (SSP), and an associated extension register (SPH) are the CPU stack registers When accessing the data stack, the CPU concatenates SPH with SP to form an extended SP that is called XSP. XSP contains the address of the value last pushed onto the data stack. SPH holds the 7-bit main data page of memory, and SP points to the specific word on that page.

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Stack Register Accesses

XSP Extended data stack pointer is accessible via dedicated instructions only. XSP is not a register mapped to memory. SP Data stack pointer is accessible via dedicated instructions and as a memorymapped register XSSP Extended system stack pointer is accessible via dedicated instructions only. XSSP is not a register mapped to memory. SSP System stack pointer is accessible via dedicated instructions and as a memorymapped register SPH High part of XSP and XSSP is accessible via dedicated instructions and as a memorymapped register.

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Program Flow Registers (PC, RETA, CFCT)

PC Program counter is a 24-bit register holds the address of the 1 to 6 bytes of code being decoded in the I unit. When the CPU performs an interrupt or call, the current PC value (the return address) is stored on the stack, and then PC is loaded with a new address. When the CPU returns from an interrupt service routine or a called subroutine, the return address is restored to PC.

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RETA Return Address Register CFCT Control-flow Context Register If the selected stack configuration uses the fast-return process

RETA is a temporary holding place for the return address and CFCT is a temporary holding place for the 8-bit loop context while a subroutine is being executed CFCT, along with RETA, enables the efficient execution of multiple layers of subroutines You can read from or write to RETA and CFCT as a pair with dedicated, 32-bit load and store instructions. The Loop context is stored into CFCT, when an interrupt or a subroutine call occur the loop context is stored in CFCT and restored on return.

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Registers For Managing Interrupts

IVPD Point to the DSP interrupt vectors (IV0IV15 and IV24IV31) IVPH Point to the host interrupt vectors (IV16IV23) IFR0, IFR1 Indicate which maskable interrupts have been requested IER0, IER1 Enable or disable maskable interrupts DBIER0, DBIER1 Configure select maskable interrupts as time-critical interrupts

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Interrupt Vector Pointers (IVPD, IVPH)

Two 16-bit interrupt vector pointers (IVPD and IVPH) point to interrupt vectors in program space.

The DSP interrupt vector pointer (IVPD) points to the 256-byte program page that contains the DSP interrupt vectors (IV0IV15 and IV24IV31). These vectors can be mapped to memory that is allocated to the DSP only. The host interrupt vector pointer (IVPH) points to the 256-byte program page that contains the host interrupt vectors (IV16IV23). These vectors can be mapped to memory shared by the DSP and the host processor, so that the host processor can define the associated interrupt service routines. If IVPD and IVPH have the same value, all of the interrupt vectors will be in the same 256-byte program page.

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Interrupt Flag Registers (IFR0, IFR1)

The 16-bit interrupt flag registers, IFR1 and IFR0, contain flag bits for all the maskable interrupts:

When a maskable interrupt request reaches the CPU, the corresponding flag is set to 1 in one of the IFRs. This indicates that the interrupt is pending, or waiting for acknowledgement from the CPU. One can read IFRs to identify pending interrupts, and write to the IFRs to clear pending interrupts. To clear an interrupt request write a 1 to the corresponding IFR bit. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. Acknowledgement of a hardware interrupt request also clears the corresponding IFR bit. A device reset clears all IFR bits.

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RTOSINTF Bit in IFR1

RTOSINTF bit 10 in IFR1 is an interrupt flag bit for the real-time operating system interrupt, RTOSINT

When you read the RTOSINTF bit,

If RTOSINTF=0, RTOSINT is not pending. If RTOSINTF=1, RTOSINT is pending.

To clear this flag bit to 0 (and clear its corresponding interrupt request), write a 1 to the bit.

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DLOGINTF and BERRINTF Bits in IFR1

DLOGINTF is the bit 9 of IFR1 for the datalog interrupt, If DLOGINTF bit is: 0 then DLOGINT is not pending. 1 then DLOGINT is pending. BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the bus error interrupt, BERRINT If BERRINTF bit is: 0 then BERRINT is not pending. 1 then BERRINT is pending. To clear these flags to 0 (and clear the corresponding interrupt request), write a 1 to the bit.

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IF16IF23 Bits in IFR1 /IF2IF15 Bits in IFR0

These are flag bits in IFR1 or IFR0 If Interrupt flag IFx is:

0 then the interrupt associated with interrupt vector x is not pending. 1 then the interrupt associated with interrupt vector x is pending.

To clear a flag bit to 0 (and clear its corresponding interrupt request), write a 1 to the bit.

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Interrupt Enable Registers (IER0, IER1)

To enable a maskable interrupt, set its corresponding bit in IER0 or IER1 to 1. To disable a maskable interrupt, clear its corresponding enable bit to 0. At reset, all the IER bits are cleared to 0, disabling all the maskable interrupts. IER1 and IER0 are not affected by a software reset instruction or by a DSP hardware reset. Initialize these registers before you globally enable (INTM = 0) the maskable interrupts.

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RTOSINTE, DLOGINTE, BERRINTE and IE16IE23 Bits in IER1 & IE2IE15 Bits in IER0 RTOSINTE is the Enable bit for the real-time operating system interrupt,RTOSINT DLOGINTE is the Enable bit for the data log interrupt, DLOGINT BERRINTE is the Enable bit for the bus error interrupt, BERRINT IE16IE23 bits are enable flags interrupt associated with interrupt vector x. IE2IE15 bits are enable flags interrupt associated with interrupt vector x.

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Debug Interrupt Enable Registers (DBIER0, DBIER1)

DBIER1 and DBIER0 are used only when the CPU is halted in the real-time emulation mode of the debugger. A maskable interrupt enabled in a DBIER is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are timecritical interrupts that are also enabled in an interrupt enable register (IER1 or IER0). Write the DBIERs to enable or disable timecritical interrupts. To enable an interrupt, set its corresponding bit.

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Registers for Controlling Repeat Loops

Single-Repeat Registers (RPTC, CSR) Block-Repeat Registers (BRC01, BRS1, RSA01, REA01) These CPU registers are mapped in memory

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Status Registers (ST0_55ST3_55)

The four 16-bit registers (ST0_55, ST1_55, ST2_55 and ST3_55) contain control bits and flag bits Control bits affect the operation of the C55x DSP Flag bits reflect the current status of the DSP or indicate the results of operations. ST0_55, ST1_55, and ST3_55 are each accessible at two addresses

At one address, all the TMS320C55x bits are available. At the other address (the protected address), some of the bits cannot be modified. The protected address is provided to support TMS320C54x code that was written to access ST0, ST1, and PMST (the C54x counterpart of ST3_55).

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Contents of Status Registers

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ST0_55 Contents

ACOV0, ACOV1, ACOV2, and ACOV3 bits give for each of the four accumulators its own overflow flag CARRY: this bit is the Carry/borrow detection and depends on the M40 bit in ST1_55:

M40 = 0: Carry/borrow is detected with respect to bit position 31. M40 = 1: Carry/borrow is detected with respect to bit position 39.

For compatibility with TMS320C54x code, make sure M40 = 0.

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DP Status Bits in ST0_55

DP is a copy in ST0_55 of the 9 most significant bits of the data page register (DP) This 9-bit field is provided for compatibility with the TMS320C54x DSPs. TMS320C55x DSPs have a data page pointer independent of ST0_55.

Any change to bits 157 of the data page register DP(157) is reflected in the DP status bits. Any change to the DP status bits is reflected in DP(157).

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TC1 and TC2 Bits of ST0_55

TC1 and TC2 are Test/Control flag The main function of a test/control bits is to hold the result of a test performed by specific instructions. All the instructions that affect a test/control flag allow you to choose whether TC1 or TC2 is affected. TCx (where x = 1 or 2) or a Boolean expression of TCx can be used as a trigger in any conditional instruction. You can clear and set TC1 and TC2 with the following instructions:
o o o o

BCLR TC1 ; Clear TC1 BSET TC1 ; Set TC1 BCLR TC2 ; Clear TC2 BSET TC2 ; Set TC2

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ASM Bit Field of ST1_55

ASM is the Accumulator shift mode bit In the TMS320C54x-compatible mode , ASM supplies a shift value in the range 16 through 15 (5 bits in 2s complement). If C54CM=1: C54x code running on the C55x DSP, and ASM contains the shift count for instructions that specify a shift of an accumulator value. If C54CM = 0: ASM is ignored and the shift count for an accumulator shift operation comes from the temporary register (T0, T1, T2, or T3) specified in the C55x instruction or from a constant embedded in the C55x instruction.

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BRAF Bit of ST1_55

BRAF: Block-repeat active flag is used in the TMS320C54x-compatible mode (C54CM = 1). BRAF indicates/controls the status of a block-repeat operation. If C54CM = 1 (C54x mode): BRAF is saved and restored with ST1_55 during context switches caused by calls, interrupts, and returns. BRAF is automatically cleared when a far branch (FB) or far call (FCALL) instruction is executed. If C54CM = 0: BRAF is not used. The status of repeat operations is maintained automatically by the CPU (see CFCT ) To stop or set an active block-repeat operation in the C54x-compatible mode, you can use the following instruction:

BCLR BRAF ; Clear BRAF BSET BRAF ; Set BRAF

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C16 Bit of ST1_55

C16 is the Dual 16-bit arithmetic mode bit used in the C54x-compatible mode (C54CM = 1), execution of some instructions is affected by C16. The arithmetic performed in the D-unit ALU depends on C16:

If C16 =0 then for an instruction that is affected by C16, the D-unit ALU performs one 32-bit operation (double-precision arithmetic) . If C16=1 then an instruction that is affected by C16, the D-unit ALU performs two 16-bit operations in parallel (dual 16-bit arithmetic).

If C54CM = 0: The CPU ignores C16. The instruction alone determines whether dual 16-bit arithmetic or 32-bit arithmetic is used.
You can clear and set C16 with the following instructions:

BCLR C16 ; Clear C16 BSET C16 ; Set C16

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C54CM Bit of ST1_55

C54CM is the TMS320C54x-compatible mode bit The C54CM bit determines whether the CPU will support code that was developed for a TMS320C54x DSP: If C54CM=0 then the CPU supports code written for a TMS320C55x (C55x) DSP. If C54CM=1 then you can use code that was originally developed for a TMS320C54x (C54x) DSP. In C54 mode all the C55x CPU resources remain available; the additional features on the C55x can be used for code optimization. Change modes with the following instructions and assembler directives:

BCLR C54CM ; Clear C54CM (happens at run time) BSET C54CM ; Set C54CM (happens at run time)

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CPL Bit of ST1_55

CPL is the Compiler mode bit and determines which of two direct addressing modes is active: CPL=0 then Direct accesses to data space are made relative to the data page register (DP). CPL=1 then Direct accesses to data space are made relative to the data stack pointer (SP). The DSP is said to be in compiler mode. Change modes with the following instructions and assembler directives: BCLR CPL ; Clear CPL (happens at run time) BSET CPL ; Set CPL (happens at run time)

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FRCT Bit of ST1_55

FRCT is the Fractional mode bit that sets the fractional mode on or off: FRCT=0 then results of multiply operations are not shifted. FRCT=1 then results of multiply operations are shifted left by 1 bit for decimal point adjustment.

This is required when you multiply two signedQ15 values and you need a Q31 result.
BCLR FRCT ; Clear FRCT BSET FRCT ; Set FRCT

You can clear and set FRCT with :

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HM Bit of ST1_55

HM is the Hold mode bit used when the DSP acknowledges an active HOLD signal. It places its external interface in the highimpedance state. Depending on HM, the DSP may also stop internal program execution: HM=0 then the DSP continues executing instructions from internal program memory. HM=1 then the DSP stops executing instructions from internal program memory. To clear and set HM:

BCLR HM ; Clear HM BSET HM ; Set HM

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INTM Bit of ST1_55

INTM is the Interrupt mode bit, it globally enables or disables the maskable interrupts. If INTM =0 All unmasked interrupts are enabled. If INTM=1 All maskable interrupts are disabled. Software interrupt instruction and software reset instruction, set INTM before branching to the interrupt service routine. Before executing an interrupt service routine (ISR), the CPU automatically sets the INTM bit to globally disable the maskable interrupts. The ISR can reenable the maskable interrupts by clearing the INTM bit. BCLR INTM ; Clear INTM BSET INTM ; Set INTM A return-from-interrupt instruction restores the INTM bit from the data stack.

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M40 Bit of ST1_55

M40 is the computation mode bit for the D unit M40 bit selects one of two computation modes for the D unit: If M40=0 then the sign bit is extracted from bit position 31:

During arithmetic, the carry is determined with respect to bit position 31. Overflows are detected at bit position 31. During saturation, the saturation value is 00 7FFF FFFFh (positive overflow) or FF 8000 0000h (negative overflow). Accumulator comparisons versus 0 are done using bits 310. Shift or rotate operations are performed on 32-bit values.

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M40 Bit

Note: In the TMS320C54x compatible mode (C54CM = 1), CM=0

An accumulators sign bit is extracted from bit position 39. Accumulator comparisons versus 0 are done using bits 390. Signed shifts are performed as if M40 = 1.

M= 40-bit mode. In this mode the sign bit is extracted from bit position 39, the same as before on 40 bits. To clear and set M40 :

BCLR M40 ; Clear M40 BSET M40 ; Set M40

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SATD Bit of ST1_55

SATD is the Saturation mode bit, it determines whether the CPU saturates overflow results in the D unit: SATD =0 No saturation is performed. SATD=1 If an operation result gives an overflow, the result is saturated. The saturation depends on the value of the M40 bit:

M40 = 0 The CPU saturates the result to 00 7FFF FFFFh (positive overflow) or FF 8000 0000h (negative overflow). M40 = 1 The CPU saturates the result to 7F FFFF FFFFh (positive overflow) or 80 0000 0000h (negative overflow). BCLR SATD ; Clear SATD BSET SATD ; Set SATD

To clear and set SATD :

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SXMD Bit of ST1_55

SXMD is the Sign-extension mode bit. It sets and resets the sign-extension mode, which affects accumulator operations that are performed in the D unit: If SXMD=0 then sign-extension mode is off: For 40-bit operations, 16-bit or smaller operands are zero extended to 40 bits. For the conditional subtract instruction, any 16-bit divisor produces the expected result. When the D-unit arithmetic logic unit (ALU) is locally configured in its dual 16-bit mode, 16-bit values used in the higher part of the Dunit ALU are zero extended to 24 bits.

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SXMD

If SXMD=1 then 40-bit operations, 16-bit or smaller operands are sign extended to 40 bits. When the D-unit ALU is locally configured in its dual 16-bit mode, 16-bit values used in the higher part of the D-unit ALU are sign extended to 24 bits. 16-bit accumulator halves are sign extended if they are shifted right. During a signed shift of an accumulator, if it is a 32bit operation (M40 = 0), bit 31 is copied into the accumulators guard bits (3932). Set and reset SXMD by:

BCLR SXMD ; Clear SXMD BSET SXMD ; Set SXMD

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XF Bit of ST1_55

The XF bit is a general-purpose output bit that can be manipulated by software and exported to XF pin of the DSP To clear and set XF:
BCLR XF ; Clear XF BSET XF ; Set XF

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AR0LCAR7LC Bits of ST2_55

AR0LCAR7LC Bits are the linear/circular configuration bits of the eight auxiliary registers, AR0AR7.
If ARnLC= 0 ARn is used for linear addressing If ARnLC=1 ARn is used for circular addressing

To clear and set the ARnLC bits

BCLR AR0LC ; Clear AR0LC BSET AR0LC ; Set AR0LC

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ARMS Bit of ST2_55

ARMS AR mode switch bit determines the CPU mode used for the AR indirect addressing mode: ARMS=0 DSP mode operands , provides efficient execution of DSP intensive applications. Among these operands are those that use reverse carry propagation when adding to or subtracting from a pointer. Short-offset operands are not available. ARMS=1 Control mode operands , enables optimized code size for control system applications. The short-offset operand *ARn(short(#k3)) is available.

BCLR ARMS ; Clear ARMS (happens at run time) .ARMS_off ; Tell assembler ARMS = 0 BSET ARMS ; Set ARMS (happens at run time) .ARMS_on ; Tell assembler ARMS = 1

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CDPLC Bit of ST2_55

CDPLC is the CDP linear/circular configuration bit. It determines whether the coefficient data pointer (CDP) is used for linear addressing or circular addressing:
CDPLC=0 Linear addressing CDPLC=1 Circular addressing

To clear and set CDPLC :

BCLR CDPLC ; Clear CDPLC BSET CDPLC ; Set CDPLC

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DBGM Bit of ST2_55

DBGM: Debug mode bit gives the ability to block debug events during time-critical portions of a program: If DBGM=0 Debug is enable If DBGM=1 Debug is disable, emulator cannot access memory or registers. Software breakpoints still cause the CPU to halt, but hardware breakpoints or halt requests are ignored. Before interrupt service routine CPU sets the DBGM bit to disable. Return-from-interrupt instruction restores the DBGM bit from the data stack.

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EALLOW Bit of ST2_55 /RDM Bit of ST2_55

EALLOW is the Emulation access enable bit. It enables or disables write access to non-CPU emulation registers:

If EALLOW =0 Emulation access is disabled If EALLOW=1 Emulation is enabled

RDM, Rounding mode bit, defines the type of rounding performed by the CPU:

If RDM =0 the mode is Round to the infinite. CPU adds 8000h (215 ) to the operand then clears bits 15 through 0 to generate a rounded result in a 24- or 16-bit representation.

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Round Mode RDM

If RDM=1 then Round to the nearest. The rounding depends on bits 15 through 0 of the operand, and bits 150 are cleared For compatibility with TMS320C54x code, RDM must be 0 and C54CM = 1. To clear or set BCLR RDM ; Clear RDM BSET RDM ; Set RDM

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CACLR Bit of ST3_55

CACLR, Cache clear bit, enables to check when the process for clearing the program cache is complete:

CACLR=0 Complete. The cache hardware clears the CACLR bit when the process is complete. CACLR=1 Not complete. All cache blocks are invalid. The number of cycles needed to clear the cache depends on the memory architecture.

If cache is cleared, the content of the prefetch queue in the instruction buffer unit is automatically flushed. CACLR bit can be changed (pipeline protect):

BCLR CACLR ; Clear CACLR BSET CACLR ; Set CACLR

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CAEN Bit of ST3_55

CAEN is the Cache enable bit that enables or disables the program cache: CAEN =0 then cache is disabled. All program requests are handled either by the internal memory or the external memory, depending on the address decoded. CAEN=1 Cache is enabled. Program code is fetched from the cache, from the internal memory, or from the external memory, depending on the address decoded.

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CAFRZ Bit of ST3_55

CAFRZ is Cache freeze bit that freezes the program cache. IF CAFRZ =0, the cache is in its default operating mode (updated) If CAFRZ=1, the cache is frozen (the cache content is locked). To change CAFRZ bit use:

BCLR CAFRZ ; Clear CAFRZ BSET CAFRZ ; Set CAFRZ

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CBERR Bit of ST3_55

CBERR is the CPU bus error flag The CBERR bit is set when an internal bus error is detected. An error causes the CPU to set the bus error interrupt flag (BERRINTF) in IFR1. The interrupt service routine for the bus error interrupt (BERRINT) must clear the CBERR bit before it returns control to the interrupted program using: BCLR CBERR ; Clear CBERR If CBERR =0 The flag has been cleared by program or by a reset. CBERR=1 An internal bus error has been detected.

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CLKOFF Bit of ST3_55

CLKOFF bit disables CLKOUT If CLKOFF = 1, the output of the CLKOUT pin is disabled and remains at a high level. Set and clear by:
BCLR CLKOFF ; Clear CLKOFF BSET CLKOFF ; Set CLKOFF

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HINT Bit of ST3_55

HINT: Host interrupt bit is used to send an interrupt request to a host processor by the way of the host port interface. To produce an active-low interrupt pulse clear and then set the HINT bit: BCLR HINT ; Clear HINT BSET HINT ; Set HINT

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MPNMC Bit of ST3_55

MPNMC defines the Microprocessor / Microcomputer mode MPNMC reflects the logic level on the MP/MC pin when the pin is sampled at reset

The MPNMC bit enables or disables the on-chip

ROM. If MPNMC=0 Microcomputer mode. The on-chip
ROM is enabled; it is addressable in program space. If MPNMC=1 Microprocessor mode. The on-chip ROM is disabled; it is not in the program-space map.

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SATA Bit of ST3_55

SATA is the Saturation mode bit for the A unit SATA bit determines whether the CPU saturates overflow results of the A-unit arithmetic logic unit (A-unit ALU): If SATA=0 No saturation is performed. If SATA=1 On. If result is in overflow, result is saturated to 7FFFh or 8000h (for positive or negative overflow respectively). Can be cleared and set by:

BCLR SATA ; Clear SATA BSET SATA ; Set SATA

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SMUL Bit of ST3_55

SMUL is the Saturation-on-multiplication mode bit: If SMUL =0 Off If SMUL =1 On. SMUL=1 forces the product of the two negative numbers to be a positive number. For multiply-and-accumulate/subtract instructions, the saturation is performed after the multiplication and before the addition/subtraction.
Clear and set SMUL with :

BCLR SMUL ; Clear SMUL BSET SMUL ; Set SMUL

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SST Bit of ST3_55

SST is the Saturate-on-store mode bit used in the C54-compatible mode (C54CM=1) If C54CM=0 SST is ignored by the C55x. If C54CM = 1: SST turns the saturation-onstore mode on or off. SST= 0 no saturation SST=1 CPU saturates a shifted or unshifted accumulator value before storing it. The saturation depends on the value of the signextension mode bit (SXMD)

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