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by National Institute of Standards and Technology (NIST) on May 26, 2002. AES is a simple design, a high speed algorithm, with low memory costs. AES is a symmetric block cipher.
The same key is used to encrypt and decrypt the message. The plain text and the cipher text are the same size.
AES
ABCDEFGHIJKLMNOP
A B C D E F G H I J K L M N O P
(ASCII)
41 42 43 44
45 46 47 48
49 4A 4B 4C
4D 4E 4F 50
AES
11 55 99 CC 11 55 99 CC
22 66 00 DD 22 66 00 DD
33 77 AA EE 33 77 AA EE
44 88 BB FF 44 88 BB FF
Expanded Key Length Key Length Block Size Number of (words) (Nk words) (Nb words) Rounds Nr AES-128 4 44 4 10 AES-192 6 52 4 12 AES-256 8 60 4 14 4 10 Rijndael - 128 4 44 6 12 8 14 4 12 Rijndael - 192 6 52 6 12 8 14 4 14 Rijndael - 256 8 60 6 14 8 14 * DES 256 2 16 2 * of 64 bits, only 56 are used
The
Assuming that one could build a machine that could recover a DES key in a second (i.e., try 255 keys per second), then it would take that machine approximately 149 thousand-billion (149 trillion) years to crack a 128-bit AES key. To put that into perspective, the universe is believed to be less than 20 billion years old.
Accepting Moore's Law, doubling processor speed every 18 months, AES will be secure for another 109.5 years.
AES
Multiplication in GF(28) consists of multiplying two polynomials modulo an irreducible polynomial of degree 8.
AES uses the following irreducible polynomial
m(x) = x8 + x4 + x3 + x + 1
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
The
11 55 99 CC
22 66 00 DD
33 77 AA EE
44 88 BB FF
i = Nk // Nk = 4 while (i < Nb*(Nr+1)) { // Nb*(Nr+1)= 4*(10+1)= 44 temp = w[ i 1] If ( i%Nk == 0 ) rotate word left 1 byte process each byte through sbox XOR with RCON[i/Nk-1] // just first byte of w[i] w[ i ] = w[ i-4 ] XOR temp i++}
If ( i%Nk == 0 ) temp = CC DD EE FF temp = DD EE FF CC rotate word left 1 byte process each byte through sbox temp = sbox[DD] sbox[EE] sbox[FF] sbox[CC] = C1 28 16 4B XOR with RCON[i/Nk-1] RCON[0] = 01
temp = (C1 temp = C0 01) 28 16 28 16 4B 4B
i xi
0 0x01
1 0x02
5 0x20
6 0x40
7 0x80
i xi
8 0x1b
D 0x4d
E 0x9a
rCon can be implemented with a look-up-table 2i in GF(28) Removes symmetry and linearity from key expansion.
i = Nk // Nk = 4 i=4 while (i < Nb*(Nr+1)) {// Nb*(Nr+1)= 4*(10+1)= 44 temp = W[i-1] If (i%Nk == 0) rotate word left 1 byte process each byte through sbox XOR with RCON[i] // just first element of w w[i] = w[i-4] XOR temp temp = C0 28 i++}
16
4B
11 55 99 CC D1
22 66 00 DD 0A
33 77 AA EE 25
44 88 BB FF 0F
i = Nk // Nk = 4 i=5 while (i < Nb*(Nr+1)) { // Nb*(Nr+1)= 4*(10+1)= 44 temp = w[i1] If (i%Nk == 0) temp = w[4] = D1 0A 25 0F rotate word left 1 byte process each byte through sbox XOR with RCON[i/Nk-1] // just first element of W w[i] = w[i-4] XOR temp i++}
11 55 99 CC D1
22 66 00 DD 0A
33 77 AA EE 25
44 88 BB FF 0F
i=5 temp = D1 0A 25 0F w[i] = w[i-4] XOR temp w[5] = (55 D1) (66 0A) (77 25) w[5] = 84 C6 52 87 (88 0F)
C1 28 16 4B
C0 28 16 4B
C8 47 2E 3E
CA 47 2E 3E
B0 A9 3B ED
B4 A9 3B ED
92 D2 D3 F8
9A D2 D3 F8
76 27 C5 B1
66 27 C5 B1
90 66 40 A9
B0 66 40 A9
B8 68 E1 11
F8 68 E1 11
9C 0B 6C D4
1C 0B 6C D4
F2 D1 66 D6
E9 D1 66 D6
A0 D5 49 58
96 D5 49 58
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
41 42 43 44
45 46 47 48
State
49 4A 4B 4C 4D 4E 4F 50
41 11 42 22 43 33 44 44
45 55 46 66 47 77 48 88
49 99 4D CC 4A 00 4E DD 4B AA 4F EE 4C BB 50 FF
After AddRoundKey
50 60 70 00 10 20 30 C0 D0 4A E1 F7 81 93 A1 AF
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
SubBytes
is the SBOX for AES This make AES a non-linear cryptographic system. For every value of b there is a unique value for b
1 1 1 1 1 0 0 0
0 1 1 1 1 1 0 0
0 0 1 1 1 1 1 0
0 0 0 1 1 1 1 1
1 0 0 0 1 1 1 1
1 1 0 0 0 1 1 1
1 1 1 0 0 0 1 1
1 1 1 1 0 0 0 1
x0 x1 x2 x3 x4 x5 x6 x7
1 1 0 0 0 1 1 0
Y 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 63 ca b7 4 9 53 d0 51 cd 60 e0 e7 ba 70 e1 8c 1 7c 82 fd c7 83 d1 ef a3 0c 81 32 c8 78 3e f8 a1 2 77 c9 93 23 2c 0 aa 40 13 4f 3a 37 25 b5 98 89 3 7b 7d 26 c3 1a ed fb 8f ec dc 0a 6d 2e 66 11 0d 4 f2 fa 36 18 1b 20 43 92 5f 22 49 8d 1c 48 69 bf 5 6b 59 3f 96 6e fc 4d 9d 97 2a 6 d5 a6 3 d9 e6 6 6f 47 f7 5 5a b1 33 38 44 90 24 4e b4 f6 8e 42 7 c5 f0 cc 9a a0 5b 85 f5 17 88 5c a9 c6 0e 94 68 8 30 ad 34 7 52 6a 45 bc c4 46 c2 6c e8 61 9b 41 9 1 d4 a5 12 3b cb f9 b6 a7 ee d3 56 dd 35 1e 99 a 67 a2 e5 80 d6 be 2 da 7e b8 ac f4 74 57 87 2d b 2b af f1 e2 b3 39 7f 21 3d 14 62 ea 1f b9 e9 0f c fe 9c 71 eb 29 4a 50 10 64 de 91 65 4b 86 ce b0 d d7 a4 d8 27 e3 4c 3c ff 5d 5e 95 7a bd c1 55 54 e ab 72 31 b2 2f 58 9f f3 19 0b e4 ae 8b 1d 28 bb f 76 c0 15 75 84 cf a8 d2 73 db 79 8 8a 9e df 16
State
50 60 70 00 10 20 30 C0 D0 4A E1 F7 81 93 A1 AF Sbox( 50 ) Sbox( 60 ) Sbox( 70 ) Sbox( 00 ) Sbox( 10 ) Sbox( 20 ) Sbox( 30 ) Sbox( C0 ) Sbox( D0 ) Sbox( 81 ) Sbox( 4A ) Sbox( 93 ) Sbox( E1 ) Sbox( A1 ) Sbox( F7 ) Sbox( AF )
53 D0 51 63
CA B7 04 BA
70 D6 F8 68
0C DC 32 79
KeyExpansion(byte key[4*Nk],word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
Simple
routine which performs a left shift rows 1, 2 and 3 by 1, 2 and 3 bytes respectively
53 B7 F8 79 CA D6 32 63 70 DC 51 BA 0C D0 04 68
53 D0 51 63
CA B7 04 BA
70 D6 F8 68
0C DC 32 79
KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)],Nk) Cipher(byte in[4*Nb],byte out[4*Nb],word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb-1]) for round = 1 step 1 to Nr1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state,w[round*Nb,(round+1)*Nb-1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb-1]) out = state end
This
with shift rows provides diffusion The columns are considered polynomials over GF(28) and multiplied modulo x4+1 with a(x) where a(x) = {03}x3 + {01}x2 + {01}x + {02} NOTE: x4+1 is relatively prime to a(x) aj (aj*a(x))mod(x4+1) This can also be written as matrix multiplication. a 0 02 03 01 01 a0
a 1 a
2
01 02 03 01 01 01 02 03 03 01 01 02
a1 a2
a3
a 3
a0 a1 a
02 03 01 01
a0 a1
a1 = a0 a 1 3a+ a 2 = a0 + 2a+ 2a2 2 3a3 01 01 02 03 a2 1 2 a3 a3 = 3a0 + a1 + a2 + 2a3 a3 03 01 01 02 a3 a 2 = a0 a1 2a2 3a3 Addition is easy in GF(28) : Addition is just the XOR operation a3 one is identity Multiplication by 1 is easy in GF(28) : Multiplication by = 3a0 thea1 a2
01 02 03 01
a0 = 2a0 + 3a1 + a2 + a3 1 a2 a3 = a + 2a + 3a + a a
1 0 1 2 3
2a3 Multiplication by 2 in GF(28) takes some work: . If multiplying by a value < 0x80 just shift all the bits left by 1 . If multiplying by a value 0x80 shift left by 1 and XOR with 0x1b . This prevents overflow and keeps the values within range
To Multiply by 3 in GF(28) : a * 0x03 = a * (0x02 + 0x01) = (a * 0x02) (a * 0x01)
KeyExpansion(byte key[4*Nk], word w[Nb* (Nr+1)],Nk) Cipher(byte in[4*Nb], byte out[4*Nb], word w[Nb*(Nr+1)]) begin byte state[4,Nb] state = in AddRoundKey(state, w[0, Nb -1]) for round = 1 step 1 to Nr 1 SubBytes(state) ShiftRows(state) MixColumns(state) AddRoundKey(state, w[round*Nb, (round+1)*Nb -1]) end for SubBytes(state) ShiftRows(state) AddRoundKey(state, w[Nr*Nb, (Nr+1)*Nb -1]) out = state end
Input String
Key
Encryption
PlainText
Decryption
Cipher Text 1st Round
RoundKey
RoundKey*
AddRoundKey InvShiftRows
1st Round
Repeat Nr -1 Round
Repeat Nr -1 Round
RoundKey
AddRoundKey SubBytes
ShiftRows
RoundKey
InvSubBytes AddRoundKey
Last Round
AddRoundKey
CipherText
How
If
plaintext messages are not divisible by 16 bytes. Padding may be a solution. An easy method is to add a single 1 bit at the end of the message followed by enough 0s to fill the block.
If the block is filled, encode one more block with a 1 followed by 0s.
Differential
Linear
Side
Channel Attacks Attacks based on studying and measuring the actual implementation of the code.
For some implementations of AES the key has been obtained in under 100 minutes.
Computer running AES was 850MHz, Pentium III running FreeBSD 4.8
Timing
Power
Avoid
rCon. Design algorithms and devices to work with constant time intervals. (independent of key and plaintext.)
Use
same memory throughout, Cache is faster than DRAM Compute Key Expansion on the fly. Utilize pipelining to stabilize CPU power consumption.
Extremely
fast compared to other block ciphers. (tradeoff between size and speed) The round transformation is parallel by design. Important in dedicated hardware. Amenable to pipelining The cipher does not use arithmetic operations so has no bias towards big or little endian architectures.
Fully
Self-supporting. Does not use Sboxes of other ciphers, bits from Rand tables, digits of or any other such jokes. Is not based on obscure or not well understood processes The tight cipher design does not leave enough room to hide a trap door.
The
inverse cipher is less suited to smart cards, as it takes more codes and cycles. The cipher and inverse cipher make use of different codes and/or tables. In hardware, The inverse cipher can only partially re-use circuitry which implements the cipher.
About AES AES Proposal : Rijndael Joan Daemen, Vincent Rijmen, 2nd version of document to NIST Polynomials in the Nations Service: Using Algebra to Design the Advanced Encryption Standard Susan Landau The Mathmatical Association of America, Monthly 111 Feb 2004 Page(s):89-117 Selecting the Advanced Encryption Standard Security & Privacy Magazine, IEEE Volume 1, Issue 2, Mar-Apr 2003 Page(s):43 - 52 Burr, W.E.;
Title: Introduction to Cryptography Author: Johannes A Buchman Publisher: Springer; 2 edition (July 13, 2004)
Security and Attacking AES Power-analysis attack on an ASIC AES implementation Ors, S.B.; Gurkaynak, F.; Oswald, E.; Preneel, B.;Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference onVolume 2, 2004 Page(s):546 - 552 Vol.2 Algebraic attacks on cipher systems Penzhorn, W.T.; AFRICON, 2004. 7th AFRICON Conference in Africa Volume 2, 2004 Page(s):969 - 974 Vol.2 Cache-Timing attacks on AES Daniel J Bernstein Preliminary version of report to National Science Foundation, grant CCR9983950
Applications / Implementations: AES A high throughput low cost AES processor Chih-Pin Su; Tsung-Fu Lin; Chih-Tsiun Huang; Cheng-Wen Wu; Communications Magazine, IEEE Volume 41, Issue 12, Dec. 2003 Page(s):86 - 91 An efficient FPGA implementation of advanced encryption standard algorithm Shuenn-Shyang Wang; Wan-Sheng Ni; Circuits and Systems, 2004. ISCAS '04. Volume 2, 23-26 May 2004 Page(s):II - 597-600 Vol.2 High-speed VLSI architectures for the AES algorithm Xinmiao Zhang; Parhi, K.K.; Very Large Scale Integration (VLSI) Systems Volume 12, Issue 9, Sept. 2004 Page(s):957 967 Fast implementation of AES cryptographic algorithms in smart cards Chi-Feng Lu; Yan-Shun Kao; Hsia-Ling Chiang; Chung-Huang Yang; Security Technology, 2003. 14-16 Oct. 2003 Page(s):573 - 579
A new VLSI implementation of the AES algorithm Liang Deng; Hongyi Chen; Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on Volume 2, 29 June-1 July 2002 Page(s):1500 - 1504 vol.2